參數(shù)資料
型號(hào)： SAA4951WP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Memory controller
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, SOT-187-2, MO-047AC, LCC-44
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 95K
代理商： SAA4951WP
April 1994
15
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
VACQ
This is the 50 Hz vertical synchronization input signal
derived from a suitable vertical synchronization circuit (i. e.
TDA2579). The LOW-to-HIGH transition of this pulse is the
timing reference of all vertical control signals of the
SAA4951.
RSTW1
The reset write output pulse 1 starts the write address
pointer of field memory 1. The RSTW1 signal is derived
from the 50 Hz vertical acquisition pulse VACQ and has a
pulse width of 64
μ
s (PAL) (see Fig.7).
Table 5
Vertical programming range of WE1 (see also Fig.7).
Nr
≠
Nf
50 Hz
V
rWE1
= Nr
×
Line
V
fWE1
= Nf
×
Line
V
rWE1
= Nr
×
Line
V
fWE1
= Nf
×
Line
1
≤
Nr
<
311
1
<
Nf
≤
311
1
≤
Nr
<
261
1
<
Nf
≤
261
60 Hz
Fig.7 Vertical acquisition timing.
handbook, full pagewidth
MGH136
VACQ
WE1
VrWE1
RSTW1
VfWE1
STROBE
The asynchronous active HIGH STROBE input controls
the input enable signals IE1 and IE2 of the memory block
in the still picture mode.
Description of display part
LLD
The input signal LLD is the main line-locked clock for the
display side of SAA4951 generated by an external PLL
circuit. Depending on the chosen application, LLD runs on
three different frequencies 12/32/36 MHz. The PLL circuit
is controlled by the horizontal deflection drive output pulse
HDFL and the horizontal reference output signal HRD
supplied by the memory controller.
SWC2
Depending on the chosen system mode the output pin
SWC2 delivers either the serial acquisition clock signal
LLA (PSC mode, 50 Hz) or the serial display clock pulse
LLD (two field memories, 100 Hz) to write the data
information into memory 2.
SRC
The display clock input signal LLD is connected through
the memory controller. LLD is internally buffered and put
out as serial read clock SRC for field memory 1.
Additionally SRC is used as clock pulse for the noise
reduction circuit NORIC and the backend circuit BENDIC.
HRD
The horizontal reference display pulse HRD has a duty
cycle of 50% and a frequency of 32 kHz. HRD is the
reference pulse for the horizontal timing of the control
signals RE1, RE2, WE2 and BLND generated by the
display circuit of SAA4951.
相關(guān)PDF資料
PDF描述
SAA4952WP Memory controller
SAA4955 2.9-Mbit field memory
SAA4955TJ 2.9-Mbit field memory
SAA4956TJ 2.9-Mbit field memory with noise reduction
SAA4960 Integrated PAL comb filter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA4952WP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Memory controller
SAA4955 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:2.9-Mbit field memory
SAA4955TJ 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:2.9-Mbit field memory
SAA4956TJ 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:2.9-Mbit field memory with noise reduction
SAA4960 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Integrated PAL comb filter
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