
April 1994
9
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
Horizontal pulses generated from the display clock
48
49
4A
4B
4C
4D
4E
BLNDSTA
BLNDSTO
HWE2STA
HWE2STO
HRESTA
HRESTO
HDMSB
start of horizontal blanking pulse (lower 8 of 9 bits)
end of horizontal blanking pulse (lower 8 of 9 bits)
start of horizontal write enable (lower 8 of 9 bits)
end of horizontal write enable (lower 8 of 9 bits)
start of horizontal read enable (lower 8 of 9 bits)
end of horizontal read enable (lower 8 of 9 bits)
bit 0: MSB of BLNDSTA
bit 1: MSB of BLNDSTO
bit 2: MSB of HWE2STA
bit 3: MSB of HWE2STO
bit 4: MSB of HRESTA
bit 5: MSB of HRESTO
bit 0: fine delay of BLND (LSB)
bit 1: fine delay of BLND (MSB)
bit 2: fine delay of HWE2 (LSB)
bit 3: fine delay of HWE2 (MSB)
bit 4: fine delay of HRE (LSB)
bit 5: fine delay of HRE (MSB)
4F
HDDEL
Vertical pulses generated from the acquisition clock
50
51
52
VWE1STA
VWE1STO
VAMSB
start of vertical write enable (lower 8 of 9 bits)
end of vertical write enable (lower 8 of 9 bits)
bit 0: MSB of VWE1STA
bit 1: MSB of VWE1STO
Horizontal pulses generated from the acquisition clock
58
59
5A
5B
5C
CLVSTA
CLVSTO
HWE1STA
HWE1STO
HAMSBDEL
start of CLV pulse
end of CLV pulse
start of horizontal write enable (lower 8 of 9 bits)
end of horizontal write enable (lower 8 of 9 bits)
bit 0: MSB of HWE1STA
bit 1: MSB of HWE1STO
bit 2: fine delay of HWE1 (LSB)
bit 3: fine delay of HWE1 (MSB)
bit 4: memory configuration bit 2 (MC2): 0 = 1050/60; 1 = 1070/2970
bit 5: WEXT (external WE)
bit 6: SFR (select field recognition)
ADDRESS
(HEX)
REGISTER
FUNCTION