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參數(shù)資料
| 型號： | SAA4951 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | RES 6.49K OHM 1/16W 0.5% 0402SMD |
| 中文描述： | 內(nèi)存控制器 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 95K |
| 代理商： | SAA4951 |
April 1994
8
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
Microcontroller interface
The SAA4951 is connected to a microcontroller via pins P0
to P7, ALE and WRD. This controller receives commands
from the I
2
C-bus and sets the registers of the
SAA4951 accordingly. Fig.4 shows the timing of these
signals. Address and data are transmitted sequentially on
the bus with the falling edge of ALE denoting a valid
address and the falling edge of WRD indicating valid data.
The individual registers, their address and their function
are listed in Table 1. Various start and stop registers are
9 bits wide, in this case the MSB is combined with other
MSBs or fine delay control bits in an extra register which
has to be addressed and loaded separately.
In order to load the proper values to the vertical write
enable registers in case of median filtering, information
about the current 100 Hz field is necessary. To obtain
these data, the microcontroller sends the address 80Hex
(READ mode) which puts the SAA4951 in output mode for
the next address / data cycle. For this one cycle the WRD
pin works as a RDN pin.
Table 1
Internal registers.
ADDRESS
(HEX)
REGISTER
FUNCTION
Vertical pulses generated from the display clock
40
41
42
43
44
45
46
VDFLSTA
VDFLSTO
VWE2STA
VWE2STO
VRE2STA
VRE2STO
VDMSB
start of VDFL pulse (lower 8 of 9 bits)
end of VDFL pulse (lower 8 of 9 bits)
start of vertical write enable (lower 8 of 9 bits)
end of vertical write enable (lower 8 of 9 bits)
start of vertical read enable (lower 8 of 9 bits)
end of vertical write enable (lower 8 of 9 bits)
bit 0: MSB of VDFLSTA
bit 1: MSB of VDFLSTO
bit 2: MSB of VWE2STA
bit 3: MSB of VWE2STO
bit 4: MSB of VRE1STA
bit 5: MSB of VRE1STO
Fig.4
μ
P-interface timing.
handbook, full pagewidth
MGH133
WRD
DATA
ADDRESS
ADDRESS
ADDRESS
DATA
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA4951WP | Memory controller |
| SAA4952WP | Memory controller |
| SAA4955 | 2.9-Mbit field memory |
| SAA4955TJ | 2.9-Mbit field memory |
| SAA4956TJ | 2.9-Mbit field memory with noise reduction |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4951WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4952WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4955 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4955TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4956TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory with noise reduction |
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