參數(shù)資料
型號: SAA4945H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: LIne MEmory noise Reduction IC LIMERIC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
文件頁數(shù): 10/20頁
文件大?。?/td> 116K
代理商: SAA4945H
1997 Jun 10
10
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Table 9
Test settings
Note
1.
X = don’t care.
SNDA, SNCL
AND
VRST (
PINS
2, 3
AND
4)
Serial interface signals
SNERT bus protocol (Synchronous No parity 8-bit receiver and Transmission bus)
SNDA is a bidirectional signal with 8-bit wide data and address (LSB first)
Serial interface signals converted (internally) to system clock domain. To avoid set-up violations these signals are
clocked two times by the system clock before further processing is performed.
Synchronization of serial address (every even byte) and data (every odd byte) by VRST.
TST2
TST1
TST0
MODE
0
X
(1)
1
X
(1)
0
1
X
(1)
X
(1)
0
X
(1)
X
(1)
1
application mode
test mode
test mode
test mode
Fig.5 Timing diagram of serial interface.
handbook, full pagewidth
MGK173
SNCL
LSB
SNDA
(receiver
mode)
SNDA
(transmitter
mode)
data
data
data
data
data
data
data
tsu(i)(D)
th(D)
td(D)
th(Q)
Tcy(SNCL)
Table 10
Timing characteristics (see Fig.5)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
t
cy(SNCL)
t
su(i)(D)
t
h(D)
t
h(Q)
t
d(D)
SNCL cycle time
input set-up time
input hold time
output data hold time
output data delay time
1
90
50
0
700
μ
s
ns
ns
ns
ns
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