參數(shù)資料
型號: SAA2520GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Stereo filter and codec for MPEG layer 1 audio applications
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 14 X 14 X 2.20 MM, PLASTIC, QFP-44
文件頁數(shù): 10/36頁
文件大小: 151K
代理商: SAA2520GP
August 1993
10
Philips Semiconductors
Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
SAA2520
Baseband Interface Signals
The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals:
SWS
SCL
SDA
FDIR
bi-directional
bi-directional
bi-directional
output
word (channel) select
bit clock
baseband data
decoding mode (direction control)
FS
64FS
Fig.10 SWS related to phase of FSYNC.
MBC148 - 1
channel
SWS
L
R
L
L
L
L
L
L
R
R
R
R
R
R
FSYNC
sub-band
31
0
1
31
0
1
The SWS signal indicates the channel of the sample signal
(either LEFT or RIGHT) and is equal to the sampling
frequency FS.
Operating at a frequency of 64 times that is used for
sampling, the bit clock dictates that each SWS period
contains 64 SDA data bits. Of these, a maximum of 36 are
used to transfer data (samples may have a length up to
18-bits). Samples are transferred most significant bit first.
Both SWS and SDA change state at the negative edge of
SCL.
This baseband data is transferred between the SAA2520
and the input/output using either Standard I
2
S (default) or
the alternative format shown in Fig.8.
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