參數(shù)資料
型號: SAA2520
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Stereo filter and codec for MPEG layer 1 audio applications
中文描述: 過濾器和立體聲的MPEG編解碼器1層音頻應(yīng)用
文件頁數(shù): 4/36頁
文件大?。?/td> 151K
代理商: SAA2520
August 1993
4
Philips Semiconductors
Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
SAA2520
PINNING
SYMBOL
PIN
DESCRIPTION
TYPE
FS256
1
(Filtered)-I
2
S clock; 256
×
sample frequency. 12 mA 3-state output + CMOS
input with pull-down
DAC control/output expander
DAC control/output expander
DAC control/output expander
supply ground (0 V)
unreliable drive processing data; CMOS level
sub-band I
2
S direction: (SWBS, SBCL, SBDA); CMOS level
sub-band I
2
S data; 4 mA, 3-state output + CMOS input with pull-down
sub-band I
2
S bit clock; 4 mA, 3-state output + CMOS input with pull-down
sub-band I
2
S word select; 4 mA, 3-state output + CMOS input with pull-down
sub-band I
2
S byte error flag; CMOS level
sub-band I
2
S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS
input with pull-down
DAI synchronization pulse
(Filtered)-I
2
S direction: (FDAC, FDAF, SDA);
reset signal for SAA2521
Filtered-I
2
S sync signal for SAA2521
Filtered-I
2
S sub-band filter data; 4 mA, 3-state output + CMOS input with
pull-down
Filtered-I
2
S sub-band codec data; 4 mA, 3-state output + CMOS input with
pull-down
I
2
S bit clock; 4 mA, 3-state output + CMOS input with pull-down
I
2
S-word select; 4 mA, 3-state output + CMOS input with pull-down
I
2
S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down
power-down mode; CMOS level
test pin
test pin
test pin
test pin
test pin
positive supply voltage (+5 V)
system reset; CMOS level with pull-down and hysteresis
test pin; do not connect
test pin; do not connect
LT interface data; 4 mA, 3-state output + CMOS input with pull-down
LT interface bit clock; CMOS level
I/O
MUTEDAC
DEEMDAC
ATTDAC
V
SS
URDA
SBDIR
SBDA
SBCL
SBWS
SBEF
SBMCLK
2
3
4
5
6
7
8
9
10
11
12
O
O
O
I
I
I/O
I/O
I/O
I
O
SYNCDAI
FDIR
FRESET
FSYNC
FDAF
13
14
15
16
17
O
O
O
O
I/O
FDAC
18
I/O
SCL
SWS
SDA
PWRDWN
DSC4
DSC3
DSC2
DSC1
DSC0
V
DD
RESET
T1
T0
LTDATA
LTCLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I/O
I/O
I/O
I
I
I/O
I
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