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參數(shù)資料
| 型號： | SAA2505H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | RES 4.99K OHM 1/16W 0.5% 0402SMD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 177K |
| 代理商： | SAA2505H |
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1998 Mar 10
14
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
I
2
C-bus control and commands (pins 63 and 64)
I
NTRODUCTION
A general description of “The I
2
C-bus and how to use it”
can be obtained from Philips sales offices using ordering
number 9398 393 40011.
For the external control of the SAA2505H a fast I
2
C-bus is
implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus. There are two
different types of control instructions:
Instructions to control the DSP program; programming
the coefficient RAM and reading the values of
parameters
Instructions controlling source selection and
programmable parts; through the control registers as
detailed in Table 3.
The detailed description of the I
2
C-bus and commands is
given in the following sections.
C
HARACTERISTICS OF THE
I
2
C-
BUS
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are the serial data
line (SDA) and the serial clock line (SCL). Both lines must
be connected to the supply rail via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz I
2
C-bus, the recommendation from Philips
Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 and 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
B
IT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 400 kHz. To be able to
run at this high frequency all of the Inputs and outputs
connected to the bus must be designed for this high speed
I
2
C-bus according the Philips specification (see Fig.5).
START
AND
STOP
CONDITIONS
Both data and clock line will remain HIGH when the bus in
not busy. A HIGH-to-LOW transition of the data line while
the clock is HIGH is defined as a STOP condition (P)
(see Fig.6).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as a START condition (S) (see Fig.6).
D
ATA TRANSFER
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.7).
A
CKNOWLEDGE
The number of data bits transferred between the START
and STOP conditions from the transmitter to the receiver
is not limited. Each byte of 8 bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level left
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to
pull-down the SDA line, left HIGH by the transmitter, during
the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse. Set-up and hold times must be taken into
account. A master receiver must signal an end-of-data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition
(see Fig.8).
S
TATE OF THE
I
2
C-
BUS INTERFACE DURING AND AFTER
POWER
-
ON RESET
During power-on reset the internal SDA line is kept HIGH
and the SDA pin is therefore high impedance. The SDA
line remains HIGH until a master pulls it down to initiate
communication.
相關PDF資料 |
PDF描述 |
|---|---|
| SAA2510 | Video CD VCD decoder |
| SAA2520GP | Stereo filter and codec for MPEG layer 1 audio applications |
| SAA2520 | Stereo filter and codec for MPEG layer 1 audio applications |
| SAA3004 | Remote control transmitter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2505H-M1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2510 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Video CD VCD decoder |
| SAA2511DEB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| SAA2520 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stereo filter and codec for MPEG layer 1 audio applications |
| SAA2520GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stereo filter and codec for MPEG layer 1 audio applications |
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