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參數(shù)資料
| 型號： | SA8028 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers |
| 中文描述： | 2.5千兆赫Σ-Δ小數(shù)N /中頻整數(shù)760兆赫的頻率合成器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 278K |
| 代理商： | SA8028 |
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Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
14
2.1
Each of the 4 word registers contains 24 programmable bits. Data is serially clocked in on the rising edge of each clock pulse with the
LSB first in, and MSB last in.
Data format
Table 3. Format of programmed data
LAST IN
MSB
SERIAL PROGRAMMING FORMAT
FIRST IN
LSB
p23
p22
p21
p20
.. / ..
.. / ..
p1
p0
2.2
Register addressing
Table 4. Register addressing
Bit
<23>
<22>
<21>
A-word address
0
0
x
B-word address
0
1
x
C-word address
1
0
x
D-word address
1
1
0
Notice that the register addresses are the MSB in each word; thus, the last to be clocked into the registers.
2.3
A-word register
Table 5. A-word, length 24 bits
Last IN
Address
<21>
Fractional ratio Kn
<20>
<19>
<18>
<17>
<16>
<15>
<14>
<13>
<12>
<11>
<10>
<9>
<8>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
0
0
K22
0
K21
0
K20
0
K19
0
Fixed to 00.
Kn sets the fractional part of the total division ratio. To avoid limit cycles the K0 bit is internally set to “1”
K18
1
K17
1
K16
0
K15
1
K14
0
K13
1
K12
1
K11
0
K10
1
K9
1
K8
1
K7
0
K6
1
K5
0
K4
0
K3
1
K2
1
K1
1
Default :
A word address
Fractional ratio select
2.3.1
The A-word register is dedicated for programming the RF loop, fractional multiplier (the sigma-delta modulator) which has an effective resolution
of 22 bits. The modulator works with 23 bits, Kn<22:0>. However, this K0 bit is set to ‘1’ internally to avoid limit cycles (cycles of less than
maximum length). This leaves 22 bits (Kn<22:1>) available for external programming. Refer to Table 6.
The fractional multiplier <A21:A0>
Calculating the desired VCO output frequency can be easily accomplished by using the following equation, Equation (1).
f
VCO
f
ref
N
2
Kn <22:1>
2
23
1
(1)
where f
ref
is the reference frequency at the REF input pin and N is the integer multiplier. K
n
, once again, is the fractional multiplier.
Example:
Determine the Kn value required for generating a VCO frequency of 2100 MHz with a reference frequency of 19.68 MHz.
Kn<22:1>
fVCO
fref
–N
2
23
2
Kn<22:1>
2100
MHz
19.68
MHz
–
106
2
23
2
2966702
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