參數(shù)資料
型號: SA8027W
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24
封裝: PLASTIC, BCC-24
文件頁數(shù): 2/22頁
文件大小: 231K
代理商: SA8027W
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2
2001 Aug 21
853–2244 26947
GENERAL DESCRIPTION
The SA8027 BICMOS device integrates programmable dividers,
charge pumps and phase comparators to implement phase-locked
loops. The device is designed to operate from 3 NiCd cells, in
pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus. The main divider is a fractional-N divider with
programmable integer ratios from 512 to 65535.
Separate power and ground pins are provided to the charge pumps
and digital circuits. The ground pins should be externally connected
to prevent large currents from flowing across the die and causing
damage. V
DDCP
must be equal to or greater than
V
DD
.
The charge pump current (gain) is fully programmable, while I
SET
is
set by an external resistance at the R
SET
pin (refer to section 1.5,
Main Output Charge Pumps and Fractional Compensation
Currents)
.
The phase/frequency detector charge pump outputs allow
for implementing a passive loop filter.
FEATURES
Low phase noise
Low power
Fully programmable main and auxiliary dividers
Programmable Normal & Integral charge pumps outputs
Fast Locking Adaptive mode design
Internal fractional spurious compensation
Hardware and software power down
Split supply for V
DD
and V
DDCP
Loop filter bandwidth programmability
APPLICATIONS
500 to 2500 MHz wireless equipment
Cellular phones (all standards)
WLAN
Portable battery-powered radio equipment.
SR01649
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
GND
CP
PON
STROBE
DATA
CLOCK
REFin+
REFin–
R
SET
AUXin
V
DDCP
PHA
10
Figure 1.
TSSOP20 Pin Configuration
13
7
2
3
4
5
6
TOP VIEW
1
8
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
CLOCK
REFin+
REFin–
SR02176
N/C
V
DDPre
GND
GND
Pre
RFin+
RFin–
GND
CP
P
P
G
P
A
N
D
S
P
L
T
V
D
C
V
DDCP
R
SET
Figure 2.
HBCC24 Pin configuration
QUICK REFERENCE DATA
SYMBOL
V
DD
V
DDCP
I
DDCP
+I
DD
I
DDCP
+I
DD
f
VCO
f
AUX
f
REF
f
PC
T
amb
PARAMETER
Supply voltage
Analog supply voltage
Supply current
Total supply current in power-down mode
Input frequency
Input frequency
Crystal reference input frequency
Maximum phase comparator frequency
Operating ambient temperature
CONDITIONS
MIN.
2.7
2.7
500
100
5
–40
TYP.
7.7
1
MAX.
3.6
3.6
2500
550
40
4
+85
UNIT
V
V
mA
μ
A
MHz
MHz
MHz
MHz
°
C
V
DDCP
Main and Aux. on
V
DD
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
TSSOP20
HBCC24
DESCRIPTION
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (Note 1)
VERSION
SOT360-1
SOT564-1
SA8027DH
SA8027W
NOTE:
1. The SA8027W will be released for production Q2, 2001.
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