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參數(shù)資料
| 型號： | SA8027W |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24 |
| 封裝： | PLASTIC, BCC-24 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 231K |
| 代理商： | SA8027W |
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
12
2.0
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 11
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
data is latched into the selected working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
SERIAL PROGRAMMING BUS
sent: C, B, and A, in that order. A typical programming sequence is
illustrated in Figure 12. Table 2 shows the format and the contents of
each word. The D word is used for testing purposes and should be
initially set to 0 for normal operation. When sending the B-word, data
bits FC7–0 for the fractional compensation DAC are not loaded
immediately. Instead they are stored in temporary registers. Only
when the A-word is loaded, these temporary registers are loaded
together with the main divider ratio.
2.1
V
DD
= V
DDCP
=+3.0 V; T
amb
= +25
°
C unless otherwise specified.
Serial bus timing characteristics
(see Figure 11)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
t
r
Input rise time
–
10
40
ns
t
f
Input fall time
–
10
40
ns
T
cy
Clock period
100
–
–
ns
Enable programming; STROBE
t
START
Delay to rising clock edge
40
–
–
ns
t
W
Minimum inactive pulse width
1/f
COMP
–
–
ns
t
SU;E
Enable set-up time to next clock edge
20
–
–
ns
Register serial input data; DATA
t
SU;DAT
Input data to clock set-up time
20
–
–
ns
t
HD;DAT
Input data to clock hold time
20
–
–
ns
Application information
SR01417
CLK
DATA
STROBE
LSB
ADDRESS
t
SU;DAT
t
HD;DAT
t
f
t
w
t
r
t
SU;E
t
START
T
cy
MSB
≥
0
Figure 11.
Serial Bus Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA8028 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers |
| SA8028W | 功能描述:鎖相環(huán) - PLL 2.5GHZ 760MHZ PLL SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SA8028W,518 | 功能描述:時(shí)鐘合成器/抖動清除器 2.5GHZ 760MHZ PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SA8028W,557 | 功能描述:鎖相環(huán) - PLL 2.5GHZ 760MHZ PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SA8028WGE | 功能描述:IC PLL FREQ SYNTHESIZER 24-HBCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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