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參數(shù)資料
| 型號： | SA8027 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
| 中文描述： | 2.5 GHz的低電壓，射頻fractional-N/IF整數(shù)頻率合成器的低功耗 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 231K |
| 代理商： | SA8027 |
Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
10
1.5
Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 8)
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R
SET
in conjunction with bits CP0,
CP1 in the C-word (see Table 1). The main charge pumps will enter
speed up mode after the A-word is set and strobe goes High. When
strobe goes Low, charge pump will exit speed up mode. The
fractional compensation is derived from the current at R
SET
, the
contents of the fractional accumulator (FRD) and by the program
value of the FDAC. The timing for the fractional compensation is
derived from the main divider.
1.6
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I
COMP
is the
compensation current and I
PUMP
is the pump current, then for each
charge pump:
Principle of Fractional Compensation
I
PUMP_TOTAL
= I
PUMP
+ I
COMP
.
The compensation is done by sourcing a small current, I
COMP
, see
Figure 9, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R
SET
, programming or speed-up operation.
For a given charge pump,
I
COMP
= ( I
PUMP
/ 128 ) * ( FDAC / 5*128) * FRD
FRD is the fractional accumulator value and is automatically
updated.
The theoretical values for FDAC are: 128 for FMOD = 1 (modulo 5)
and 80 for FMOD = 0 (modulo 8).
SR02359
REFERENCE R
MAIN M DIVIDE RATIO
CHARGE PUMP OUTPUT
ACCUMULATOR VALUE (FRD)
FRACTIONAL COMPENSATION
CURRENT (I
COMP
)
I
PUMP–TOTAL
N
N
N+1
N
N+1
2
4
1
3
0
PULSE
WIDTH
MODULATION
PULSE LEVEL
MODULATION
mA
μ
A
GRAPHS NOT TO SCALE.
NOTE:
For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump output.
Figure 8.
Waveforms for NF = 2 Modulo 5
→
fraction =
2
/
5
SR01800
f
RF
MAIN DIVIDER
FRACTIONAL
ACCUMULATOR
f
REF
I
COMP
I
PUMP
LOOP FILTER
& VCO
Σ
Figure 9.
Current Injection Concept
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| SA8027DH | 功能描述:鎖相環(huán) - PLL DUAL FRACTIONAL N SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SA8027DH,512 | 功能描述:射頻無線雜項(xiàng) DUAL FRACTIONAL N RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
| SA8027DH,518 | 功能描述:鎖相環(huán) - PLL DUAL FRACTIONAL N RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SA8027DH-T | 功能描述:鎖相環(huán) - PLL DUAL FRACTIONAL N SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SA8027W | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
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