參數(shù)資料
型號(hào): SA8025ADK
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Low-voltage 1.8GHz fractional-N synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 1800 MHz, PDSO20
文件頁(yè)數(shù): 7/23頁(yè)
文件大?。?/td> 456K
代理商: SA8025ADK
Philips Semiconductors
Product specification
SA8025A
1.8GHz low-voltage Fractional-N synthesizer
1996 Oct 15
7
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
1
f
VCO
MAX
Pulse width; STROBE
A word, PR = ‘01’
(NM2
65)
t
W
A word, PR = ‘10’
1
fVCO
[(NM2
65)
(NM3
1)
68]
tW
t
SW
A word, PR = ‘11’
1
fVCO
[(NM2
65
(NM3
1)
68
(NM4
1)
73)]
tW
ns
A word, PR = ‘00’
1
fVCO
[(NM2
65)
(NM4
1)
73]
tW
NOTES:
1. When a serial input “A” word is programmed, the main charge pumps on PHP and PHI are in the “speed up mode” as long as STROBE = H.
When this is not the case, the main charge pumps are in the “normal mode”.
2. The relative output current variation is defined thus:
I
OUT
I
OUT
|(I
2
3. F
RD
is the value of the 3 bit fractional accumulator.
4. Monotonicity is guaranteed with C
N
= 0 to 255.
5. Power supply current measured with f
RF_IN
= 1667.4MHz, NM1 = 0, NM2 = 1, NM3 = 1, NM4 = 4, FMOD = 8, N = 694 6/8, main phase
detector frequency = 2.4MHz, f
REF IN
= 19.2MHz, NR = 8, SM = 1, f
AUX_IN
= 150MHz, NA = 125, SA = 1, PA = 0, auxiliary phase detector
frequency = 300kHz, IRN = IRA = IRF = 25
μ
A, CN = 160, CL = 0, CK = 0, lock condition, normal mode, V
CCP
= V
DD
= V
DDA
= 3V.
Operational supply current = I
+ I
DD
+ I
CCP
.
6. Specification condition: CN = 255
7. Specification conditions:
1) CN = 255; CL = 1, or
2) CN = 75; CL = 3
8. Typical output current | I
PHI
| = –I
RN
x CN x 2
(CL+1)
x CK/32:
1) CN = 160; CL = 3; CK = 1, or
2) CN = 160; CL = 2; CK = 2, or
3) CN = 160; CL = 1; CK = 4, or
4) CN = 160; CL = 0; CK = 8
9. Any RFD, CL = 1 for speed-up pump. The integral pump is intended for switching only and the fractional compensation is not guaranteed.
10.Specification conditions: F
RD
= 1 to 7; CL = 1.
11. Specification conditions:
1) F
RD
= 1 to 7; CL = 1; CK = 2, or
2) F
RD
= 1 to 7; CL = 2; CK = 1.
12.The matching is defined by the sum of the P and the N pump for a given output voltage.
13.Limited analog supply voltage range 4.5 to 5.5V.
14.For f
< 50MHz, low frequency operation requires DC-coupling and a minimum input slew rate of 32V/
μ
s.
15.Guaranteed by design.
16.F
XTAL
= 14.4MHz, V
XTAL
= 500mV
P-P
, comparison Freq. = 200kHz, Loop bandwidth = 5kHz, Audio filter = 300Hz to 15kHz.
2
(I
2
I
1
)
I
1
)| with V
1
= 0.7V, V
2
= V
DDA
– 0.8V (see Figure 3).
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