參數(shù)資料
型號(hào): SA8025A
廠商: NXP Semiconductors N.V.
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: 低電壓1.8GHz的分?jǐn)?shù)N頻率合成器
文件頁(yè)數(shù): 6/23頁(yè)
文件大?。?/td> 456K
代理商: SA8025A
Philips Semiconductors
Product specification
SA8025A
1.8GHz low-voltage Fractional-N synthesizer
1996 Oct 15
6
DC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
MAX
Fractional compensation PHP, speed up mode
NO TAG, 10
V
PHP
= V
DDA
, V
RN
= V
DDA
PHP vs F
RD3
Pump leakage
Charge pump leakage currents, charge pump not active
Output leakage current PHP; normal
mode
NO TAG
Output leakage current PHI; normal
mode
NO TAG
I
PHA_L
Output leakage current PHA
I
PHP_F_S
I
RF
= –62.5
μ
A;F
RD
= 1 to 7
13
I
RF
= –25
μ
A;F
RD
= 1 to 7
–3.35
–1.35
–20
–2
–1.0
–1.1
–0.5
20
μ
A
Fractional compensation output current
nA
I
PHP_L
V
PHP
= 0.7 to V
DDA
– 0.8
0.1
20
nA
I
PHI_L
V
PHI
= 0.7 to V
DDA
– 0.8
0.1
20
nA
V
PHA
= 0.7 to V
DDA
– 0.8
0.1
20
nA
AC ELECTRICAL CHARACTERISTICS
V
DD
= V
DDA
= V
CCP
= 3V; T
A
= 25
°
C; unless otherwise specified. Test Circuit, Figure 4. The parameters listed below are tested using
automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits of the
device. Use of an optimized RF layout will improve many of the listed parameters.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
MAX
Main divider
guaranteed and tested on an automatic tester. Some performance parameters may be improved by using optimized layout.
Pin = -20dBm, Direct coupled input
14
Pin = -20dBm, 1000pF input coupling
V
RF_IN
Input sensitivity
Reference divider (V
DD
= V
DDA
= 3V or V
DD
= 3V / V
DDA
= 5V)
2.7 < V
DD
and V
DDA
< 5.5V
2.7 < V
DD
and V
DDA
< 4.5V
2.7 < V
DD
and V
DDA
< 5.5V
2.7 < V
DD
and V
DDA
< 4.5V
f
RF_IN
Input signal frequency
0
1.8
1.8
0
GHz
f
IN
= 1800MHz
–20
dBm
f
REF_IN
Input signal frequency
25
30
MHz
V
REF_IN
Input signal range, AC coupled
500
300
mV
P-P
Z
REF_IN
Reference divider input impedance
15
100
3
k
pF
Auxiliary divider
f
AUX_IN
Input signal frequency
PA = “0”, prescaler enabled
Input signal frequency
PA = “1”, prescaler disabled
Input signal range, AC coupled
0
0
0
0
50
150
30
40
MHz
4.5V
V
DDA
5.5V
4.5V
V
DDA
5.5V
V
AUX_IN
200
mV
P-P
k
pF
Z
AUX_IN
Auxiliary divider input impedance
15
100
3
Serial interface
15
f
CLOCK
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
Hold time; CLOCK to DATA
Pulse width; CLOCK
Pulse width; STROBE
In-Loop Performance
16
V
DDA
= 5V, V
DD
= 2.7V
RF
MM
Main loop residual FM
10
MHz
t
SU
30
ns
t
H
30
30
30
ns
t
W
ns
B, C, D, E words
F
VCO
= 1780MHz
600
900
Hz
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相關(guān)代理商/技術(shù)參數(shù)
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SA8025ADK 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-voltage 1.8GHz fractional-N synthesizer
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SA8027DH 功能描述:鎖相環(huán) - PLL DUAL FRACTIONAL N SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray