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參數(shù)資料
| 型號： | SA8025A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | 低電壓1.8GHz的分數(shù)N頻率合成器 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大小： | 456K |
| 代理商： | SA8025A |
Philips Semiconductors
Product specification
SA8025A
1.8GHz low-voltage Fractional-N synthesizer
1996 Oct 15
15
|I
PHI_comp
|
FRD
I
RN
128
(2
CL
1
) CK
Figure 9 shows that for proper fractional compensation, the area of
the fractional compensation current pulse must be equal to the area
of the charge pump ripple output. This means that the current
setting on the input RN, RF is approximately:
I
RN
I
RF
(Q
f
VCO
)
F
INR
)
(3
CN
where:
Q
f
VCO
= f
INM
×
N,
F
INR
=
=
fractional-N modulus
input frequency of the prescaler
input frequency of the reference divider
PHI pump is meant for switching only. Current and compensation
are not as accurate as PHP.
Lock Detect
The output LOCK is H when the auxiliary phase detector AND the
main phase detector indicates a lock condition. The lock condition
is defined as a phase difference of less than +1 cycle on the
reference input REF_IN. The lock condition is also fulfilled when the
relative counter is disabled (EM = “0” or respectively EA = “0”) for
the main, respectively auxiliary counter.
Test Modes
The lock output is selectable as f
REF
, f
AUX
, f
MAIN
and lock. Bits T1
and T0 of the E word control the selection (see Figures 6 and 10).
If T1 = T0 = Low, or if the E-word is not sent, the lock output is
configured as the normal lock output described in the Lock Detect
section.
If T1 = Low and T0 = High, the lock output is configured as f
REF
.
The signal is the buffered output of the reference divider NR and the
3-bit binary counter SM. The f
REF
signal appears as normally low
and pulses high whenever the divider reaches terminal count from
the value programmed into the NR and SM registers. The f
REF
signal can be used to verify the divide ratio of the Reference divider.
If T1 = High and T0 = Low, the lock output is configured as f
AUX
.
The signal is normally high and pulses low whenever the divider
reaches terminal count from the value programmed into the NA and
PA registers. The f
AUX
signal can be used to verify the divide ratio
of the Auxiliary divider.
If T1 = High and T0 = High, the lock output is configured as f
MAIN
.
The signal is the buffered output of the MAIN divider. The f
MAIN
signal appears as normally high and pulses low whenever the
divider reaches terminal count from the value programmed into the
NM1, NM2, NM3 or NM4 registers. The f
MAIN
signal can be used to
verify the divide ratio of the MAIN divider and the prescaler.
Test Pin
The Test pin, Pin 19, is a buffered logic input which is exclusively
ORed with the output of the prescaler. The output of the XOR gate
is the input to the MAIN divider. The Test pin must be connected to
V
DD
during normal operation as a synthesizer. This pin can be used
as an input for verifying the divide ratio of the MAIN divider; while in
this condition the input to the prescaler, RF
IN
, may be connected to
V
CCP
through a 10k
resistor in order to place prescaler output into
a known state.
MAIN
DIVIDER
REF
DIVIDER
AUX
DIVIDER
SM
LOCK
T1
T0
φ
MAIN
φ
AUX
SELECT
LOGIC
SR00561
Figure 10. Test Mode Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SA8025ADK | Low-voltage 1.8GHz fractional-N synthesizer |
| SA8026 | 2.5GHz low voltage fractional-N dual frequency synthesizer |
| SA8026DH | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| SA8027 | 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
| SA8027DH | 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA8025ADK | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-voltage 1.8GHz fractional-N synthesizer |
| SA8026 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5GHz low voltage fractional-N dual frequency synthesizer |
| SA8026DH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5GHz low voltage fractional-N dual frequency synthesizer |
| SA8027 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer |
| SA8027DH | 功能描述:鎖相環(huán) - PLL DUAL FRACTIONAL N SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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