參數(shù)資料
型號(hào): SA8016WC
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: SCSI-3 FAST WIDE 3 FT CABLE
中文描述: PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24
封裝: 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, MO-217, SOT-564-1, CSP, HBCC-24
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 252K
代理商: SA8016WC
Philips Semiconductors
Product specification
SA8016
2.5GHz low voltage fractional-N synthesizer
1999 Nov 04
7
SYMBOL
UNIT
MAX.
TYP.
MIN.
CONDITIONS
PARAMETER
Phase noise (R
SET
= 7.5 k
, CP = 00)
Synthesizer’s contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.
GSM
f
REF
= 13MHz, TCXO,
f
COMP
= 1MHz
indicative, not tested
–90
dBc/Hz
Synthesizer’s contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.
–83
dBc/Hz
(f)
Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.
TDMA
f
REF
= 19.44MHz, TCXO,
f
COMP
= 240kHz
indicative, not tested
–85
dBc/Hz
Synthesizer’s contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.
–77
dBc/Hz
Interface logic input signal levels; pins 13, 14, 15, 16
V
IH
HIGH level input voltage
0.7*V
DD
V
DD
+0.3
V
V
IL
LOW level input voltage
–0.3
0.3*V
DD
V
I
LEAK
Input leakage current
logic 1 or logic 0
–0.5
+0.5
μ
A
Lock detect output signal (in push/pull mode); pin 1
V
OL
LOW level output voltage
I
sink
= 2mA
0.4
V
V
OH
NOTES:
HIGH level output voltage
I
source
= –2mA
V
DD
–0.4
V
1. I
SET =
V
SET
R
SET
bias current for charge pumps.
2. The relative output current variation is defined as:
I
OUT
I
OUT
2
.
(I
2
–I
1
)
I(I
2
I
1
)I; with V
1
0.7V, V
2
V
DDCP
–0.8V (See Figure 4.)
I
2
I
1
I
2
I
1
V
1
V
2
CURRENT
V
PH
SR00602
I
ZOUT
Figure 4.
Relative Output Current Variation
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