參數(shù)資料
型號(hào)： SA8016WC
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： SCSI-3 FAST WIDE 3 FT CABLE
中文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24
封裝： 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, MO-217, SOT-564-1, CSP, HBCC-24
文件頁(yè)數(shù)： 10/20頁(yè)
文件大小： 252K
代理商： SA8016WC
Philips Semiconductors
Product specification
SA8016
2.5GHz low voltage fractional-N synthesizer
1999 Nov 04
10
Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 7)
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R
SET
in conjunction with bits CP0,
CP1 in the B-word (see table of charge pump ratios). The fractional
compensation is derived from the current at R
SET
, the contents of
the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.
Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I
COMP
is the
compensation current and I
PUMP
is the pump current, then for each
charge pump:
I
PUMP_TOTAL
= I
PUMP
+ I
COMP
.
The compensation is done by sourcing a small current, I
COMP
, see
Figure 8, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R
SET
, programming or speed-up operation.
For a given charge pump,
I
COMP
= ( I
PUMP
/ 128 ) * ( FDAC / 5*128) * FRD
FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and
80 for FMOD = 0 (modulo 8).
SR01416
REFERENCE R
MAIN M
DIVIDE RATIO
DETECTOR
OUTPUT
ACCUMULATOR
FRACTIONAL
COMPENSATION
CURRENT
OUTPUT ON
PUMP
N
N
N+1
N
N+1
2
4
1
3
0
PULSE
WIDTH
MODULATION
PULSE LEVEL
MODULATION
mA
μ
A
NOTE:
For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 7.
Waveforms for NF = 2 Modulo 5
→
fraction =
2
/
5
SR01682
f
1930.140 MHz
MAIN DIVIDER
N = 8042
FRACTIONAL
ACCUMULATOR
f
240 kHz
240.016 kHz
I
COMP
I
PUMP
LOOP FILTER
& VCO
FMOD
NF
Figure 8.
Current Injection Concept
相關(guān)PDF資料
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SA8025A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-voltage 1.8GHz fractional-N synthesizer
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