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參數(shù)資料
| 型號(hào)： | SA5223D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Wide dynamic range AGC transimpedance amplifier 150MHz |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AA, SOT-96-1, SOP-8 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 136K |
| 代理商： | SA5223D |
Philips Semiconductors
Product specification
SA5223
Wide dynamic range AGC transimpedance amplifier(150MHz)
1995 Oct 24
3
DC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at T
A
= 25
°
C, and V
CC
= +5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5223
Typ
1.55
3.2
80
22
2
UNIT
Min
1.3
2.9
-200
15
1.5
Max
1.8
3.5
+200
29
V
IN
V
O
±
V
OS
I
CC
I
OMAX
Input bias voltage
Output bias voltage
Output offset voltage (V
PIN6
- V
PIN7
)
Supply current
Output sink/source current
NOTE:
Standard deviations are estimated from design simulations to represent manufacturing variations over the life of the product.
V
V
mV
mA
mA
AC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at T
A
= 25
°
C and V
CC
= +5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5223
Typ
UNIT
Min
Max
R
T
Transresistance (differential output)
DC tested, R
L
=
∞
, I
IN
= 0-1
μ
A
90
125
160
k
R
T
Transresistance
(single-ended output)
Output resistance
(differential output)
Output resistance
(single-ended output)
Bandwidth (-3dB)
Input resistance
Input capacitance
1
Input capacitance including Miller multiplied
capacitance
Transresistance power supply sensitivity
Transresistance ambient temperature sensi-
tivity
RMS noise current spectral density (referred
to input)
2
DC tested, R
L
=
∞
, I
IN
= 0-1
μ
A
45
62.5
80
k
R
O
DC tested
140
R
O
DC tested
70
f
3dB
R
IN
C
IN
Test Circuit 1
DC tested
110
150
250
MHz
pF
0.7
C
INT
4.0
pF
R/
V
V
CC1
= V
CC2
= 5
±
0.5V
3
%/V
R/
T
T
A
= T
A MAX
- T
A MIN
0.09
%/
o
C
I
IN
Test Circuit 2, f = 10MHz
1.17
pA
Hz
Integrated RMS noise current over the band-
idth (referred to inp t)
width (referred to input)
= 0.1pF
C
S
= 0.1 F
Test circuit 2,
f = 50MHz
f = 100MHz
f = 150MHz
f = 50MHz
f = 100MHz
f = 150MHz
DC Tested,
V
CC
=
±
0.5V
f = 1.0MHz, Test Circuit 3
I
i
= 0–2mA peak AC
7
12
16
8
13
18
–55
–20
800
I
T
nA
C
S
= 0.4pF
PSRR
PSRR
V
OLMAX
dR
T
dt
Power supply rejection ratio (change in V
OS
)
Power supply rejection ratio
3
Maximum differential output AC voltage
dB
dB
mV
AGC loop time constant parameter
4
10
μ
A to 20
μ
A steps
1
dB/ms
I
INMAX
Maximum input amplitude for output duty
cycle of 50
±
5%
Output rise and fall times
Group delay
Test circuit 4
+2
mA
t
r
, t
f
t
D
10 – 90%
f = 10MHz
2.2
2.2
ns
ns
NOTES:
1. Does not include Miller-multiplied capacitance of input device.
2. Noise performance measured differential. Single-ended output noise is higher due to CM noise.
3. PSRR is output referenced and is circuit board layout dependent at higher frequencies. For best performance use a RF filter in V
CC
line.
4. This implies that the SA5223 gain will change 1dB (10%) in the absence of data for 1ms (i.e., can handle bursty data without degrading Bit
Error Rate (BER) for 100,000 cycles at 100MHz).
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