Philips Semiconductors Data Communications Products
Applications Note
AN4003
Fiber optic receiver applications note
October 12, 1992
6
The threshold voltage is set to 1.0V by R
1
and R
2
at Pin 16 of the
NE5224 postamplifier. As noted in Table 2 this sets the threshold
level, Vth, at 12.8mV
P-P
.
This corresponds to an input current on Pin 3 of the SA5222 of
I
IN
12.8mV
16.6 x 10
3
0.75 A
or
P
OPT
0.75
10
6
A
0.45A W
1.7 W
or –28dBmo, minimum.
C|AZ| is 0.1
μ
F for a low frequency data limit of 1KHz.
The status detector allows visual output to determine when the input
signal level is above the receiver threshold described above. The
light is on when signal level is below threshold. (Figure 8).
The Optical Receiver Board Construction
(Figure 19)
Supply decoupling is obtained by splitting up the various parts of the
receiver with 10
μ
H chokes combined with low inductance chip
capacitors placed in close proximity to the IC supply pin and
grounded to wide ground plane copper areas.
Observe that the top and bottom of the printed circuit board is
covered with copper ground plane within which the circuit traces are
embedded. In addition, the bottom and top planes are tied together
with connecting pins (soldered carefully) and placed at numerous
points around the board. In particular this must be done where
critical ground returns such as ground 1 and 2 of the SA5222 are
brought out of the SMD device. A good rule is to place top to bottom
ground plane pins every half inch in critical areas.
The supply is isolated between the input preamplifier, SA5222 and
the post amplifier, SA5224. Ground traces are also separated into
input stage (analog) and output stage (digital) grounds. This
technique provides a more stable circuit, in addition to allowing
ground referenced ECL signal into 50
loads at the output.
Noise Immunity
Level detection is set to automatically block reception when input
signals fall below the threshold.
If left disconnected the JAM function is inactive. The NE/SA5224
(100K ECL output) and the NE/SA5225 (10K ECL output) easily
provide sufficient signal detection and level translation accuracy for
100MB/s signal reproduction.
The signal-to-noise ratio is primarily determined by the receiver input
stage so that equivalent input noise versus input signal current and
signal bandwidth sets the limits on the signal-to-noise ratio of the
combined receiver.
The noise immunity of the receiver proper, including the PC board, is
determined by how well the layout is done. Ground plane
construction of the signal preamplifier and post amplifier (with regard
to RF technique) is required. No high level signal traces should be
returned near the input sections in order to prevent feedback
oscillation. The overall gain of preamplifier and post amplifier is in
excess of 100dB with very wide bandwidth. This makes physical as
well as electrical layout critical but reasonable once the rules are
understood. Good bypassing of the V
CC
lines, a low inductance
ground plane and high quality passive components are required.
Note that 1” of copper trace 1/16th” wide is equivalent to 15nH of
inductance. Wide traces on all V
CC
and ground bus connections are
mandatory. The same applies to the PIN diode signal traces at the
input stage.