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參數(shù)資料
| 型號(hào)： | SA5222 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Low-Power FDDI Transimpedance Amplifier(低功耗FDDI互阻抗放大器) |
| 中文描述： | 低功耗FDDI的互阻抗放大器（低功耗FDDI的互阻抗放大器） |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 270K |
| 代理商： | SA5222 |
Philips Semiconductors Data Communications Products
Applications Note
AN4003
Fiber optic receiver applications note
October 12, 1992
3
exception of different hysteresis specifications, the two devices are
fully pin-for-pin compatible.
Figure 5.
+V
CC
Q
1
220
DATA IN
DATA IN
Q
3
Q
4
Q
2
2mA
–V
EE
V
O1
V
O2
V
T
V
T
2V
T
2V
T
a. NE/SA5224, 5225 Simplified Input Stage Data
INPUT
0
b. NE/SA5224 Input Stage Transfer Functions
220
500
μ
A
500
μ
A
4.5k
4.5k
V
B
V
B
±
50mV
Theory of Operation*
Referring to the Operational Block Diagram in Figure 4, the device
consists of a main signal path that is fully differential from input to
output. The input amplifier consists of a differential pair limited to an
I
CC
of 2mA (see Figure 5a). The amplifier is a limiting type with gain
reduction above 2 V
t
, or about 100mV
P-P
. The input common mode
voltage is approximately 2.9V with a V
CC
of 5V. The input
resistance of the device is typically 4.5k
. This, then, allows the
calculation of the minimum coupling capacitor for the lowest data
frequency component. (See Figure 5b.)
The NE/SA5224 Postamplifier
The NE/SA5224 is designed to operate within the FDDI specification
data rate of 125Mb/s using the 4B/5B format. At 100Mb/s this
requires the data clock to operate at 62.5MHz and presumes the
use of an NRZ format. The NE/SA5224 is rated to operate over a
frequency range of 1kHz to 120MHz, but will operate higher in
frequency with some loss of sensitivity.
The first stage input capacitance is on the order of 1.5pF including
the ESD diode junction capacitance plus the input device and
package contributions.
Following the first stage are the intermediate gain stages from which
a sample of the amplified signal is fed to the level detector.
(*Unless stated, also applies to NE/SA5225.)
HYSTERESIS
V
TL (OFF)
V
TH (ON)
Figure 6.
Level Detector
This section provides the programmable threshold function of the
device. Adjustment of the voltage on Pin 16 determines the point at
which the input signal decision level occurs. The threshold levels
are rated for the single-ended voltage trip level of 2 to 12mV
P-P
which corresponds to twice this value or 4 to 24mV
P-P
differentially
(see Table 2).
Threshold sensing may be combined with the output signal function
through use of the data out Jam functions). This allows you to force
the output to a fixed state when the input falls below the
predetermined level as programmed on Pin 16. This function is
provided by connecting Pins 8 and 9 together.
Table 2.
V
SET
V
TL
V
TH
V
P-P(avg
)
5.0mV
R
1
R
2
0.5V
3.6mV
6.4mV
4050
950
1.0V
7.2mV
12.8mV
10.0mV
3110
1890
1.5V
10.8mV
19.2mV
15.0mV
2160
2840
2.0V
14.4mV
26.0mV
20.0mV
1210
37900
The signal level detector controls the status detector, which has
complimentary outputs at Pins 9 and 10. Pin 9 is forced to a high
state whenever the input to the NE/SA5224 falls below the user
determined voltage threshold as set on Pin 16 (V
SET
) (see Figure 4).
In the Jam state, the ECL data outputs are forced into
predetermined states, D
OUT
= low and D
OUT
= high. The
complimentary ST output at Pin 10 may be used as a system status
enable providing an ECL high when the input signal level is above
the threshold level.
The status circuit operates on the basis of a full wave rectifier
averaging detector with a nominal response time of 1
μ
s. Additional
filtering may be added at Pin 7, (C
F
pin) which has characteristic
internal resistance of 24k
. This allows the user to select the time
constant of the low-pass filter to meet a specific application by
adding external capacitance at this pin. Note that the capacitor is
returned to the plus V
CC
line.
The hysteresis characteristic of the NE/SA5224 is fixed internally
between 4 and 6dB. The plot in Figure 6 shows how this relates to
the threshold levels discussed above. The typical value in dB is
determined by taking 20 times the log of the ratio of V
TH
(on) to V
TL
(off) and for the NE/SA5224 this equals 5dB. The NE/SA5225,
however, has a typical hysteresis value of 3dB with a tested range of
2 to 4dB.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SA5222D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low-power FDDI transimpedance amplifier |
| SA5223 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Wide dynamic range AGC transimpedance amplifier 150MHz |
| SA5223D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Wide dynamic range AGC transimpedance amplifier 150MHz |
| SA5224 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:FDDI fiber optic postamplifier |
| SA5224D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:FDDI fiber optic postamplifier |
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