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參數(shù)資料
| 型號： | SA5212AD/01,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSIMP AMP 140MHZ 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 放大器類型： | 轉(zhuǎn)阻 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| -3db帶寬： | 140MHz |
| 電流 - 電源： | 26mA |
| 電流 - 輸出 / 通道： | 4mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 其它名稱： | 935275245112 SA5212AD/01 SA5212AD/01-ND |
Philips Semiconductors
Product specification
SA5212A
Transimpedance amplifier (140MHz)
1998 Oct 07
4
AC ELECTRICAL CHARACTERISTICS
Minimum and Maximum limits apply over operating temperature range at VCC=5V, unless otherwise specified. Typical data applies at VCC=5V
and TA=25°C5.
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
RT
Transresistance (differential output)
DC tested, RL = ∞
Test Circuit 6, Procedure 1
9.0
14
19
k
RO
Output resistance (differential output)
DC tested
14
30
46
RT
Transresistance (single-ended output)
DC tested, RL = ∞
4.5
7
9.5
k
RO
Output resistance (single-ended output)
DC tested
7
15
23
Test Circuit 1
D package,
f3dB
Bandwidth (-3dB)
TA = 25°C
100
140
MHz
N, FE packages,
TA = 25°C
100
120
RIN
Input resistance
70
110
150
CIN
Input capacitance
10
18
pF
R/V
Transresistance power supply sensitivity
VCC = 5 ±0.5V
9.6
%/V
R/T
Transresistance ambient
temperature sensitivity
D package
TA = TA MAX-TA MIN
0.05
%/
°C
IN
RMS noise current spectral density
(referred to input)
Test Circuit 2
f = 10MHz TA = 25°C
2.5
pA/
√Hz
Integrated RMS noise current over the band-
TA = 25°C Test Circuit 2
f = 50MHz
20
g
width (referred to input) CS = 01
f = 100MHz
27
IT
f = 200MHz
40
nA
T
f = 50MHz
22
CS = 1pF
f = 100MHz
32
f = 200MHz
52
PSRR
Power supply rejection ratio2
Any package
DC tested
VCC = 0.1V
Equivalent AC
Test Circuit 3
20
33
dB
PSRR
Power supply rejection ratio2
(ECL configuration)
Any package
f = 0.1MHz1
Test Circuit 4
23
dB
VO MAX
Maximum differential output voltage swing
RL = ∞
Test Circuit 6, Procedure 3
1.7
3.2
VP-P
VIN MAX
Maximum input amplitude for output duty
cycle of 50
±5%3
Test Circuit 5
325
mVP-P
tR
Rise time for 50mV output signal4
Test Circuit 5
2.0
ns
NOTES:
1. Package parasitic capacitance amounts to about 0.2pF.
2. PSRR is output referenced and is circuit board layout dependent at higher frequencies. For best performance use RF filter in VCC line.
3. Guaranteed by linearity and over load tests.
4. tR defined as 20-80% rise time. It is guaranteed by -3dB bandwidth test.
5. As in all high frequency circuits, a supply bypass capacitor should be located as close to the part as possible.
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