參數(shù)資料
型號(hào): SA5204AN
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 衰減器
英文描述: RES 110 OHM 1/10W .5% 0805 SMD
中文描述: 0 MHz - 350 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER
文件頁(yè)數(shù): 7/14頁(yè)
文件大?。?/td> 190K
代理商: SA5204AN
Philips Semiconductors
Product specification
NE/SA5204A
Wide-band high-frequency amplifier
1992 Feb 25
7
THEORY OF OPERATION
The design is based on the use of multiple feedback loops to
provide wide-band gain together with good noise figure and terminal
impedance matches. Referring to the circuit schematic in Figure 17,
the gain is set primarily by the equation:
V
OUT
V
IN
(R
F1
R
E1
)
R
E1
(1)
which is series-shunt feedback. There is also shunt-series feedback
due to R
F2
and R
E2
which aids in producing wide-band terminal
impedances without the need for low value input shunting resistors
that would degrade the noise figure. For optimum noise
performance, R
E1
and the base resistance of Q
1
are kept as low as
possible, while R
F2
is maximized.
The noise figure is given by the following equation:
NF
10Log
1
r
b
R
E1
KT
2ql
C1
R
O
dB
(2)
where I
C1
=5.5mA, R
E1
=12
, r
b
=130
, KT/q=26mV at 25
°
C and
R
0
=50 for a 50
system and 75 for a 75
system.
The DC input voltage level V
IN
can be determined by the equation:
V
IN
=V
BE1
+(I
C1
+I
C3
) R
E1
(3)
where R
E1
=12
, V
BE
=0.8V, I
C1
=5mA and I
C3
=7mA (currents rated
at V
CC
=6V).
Under the above conditions, V
IN
is approximately equal to 1V.
Level shifting is achieved by emitter-follower Q
3
and diode Q
4
,
which provide shunt feedback to the emitter of Q
1
via R
F1
. The use
of an emitter-follower buffer in this feedback loop essentially
eliminates problems of shunt-feedback loading on the output. The
value of R
F1
=140
is chosen to give the desired nominal gain. The
DC output voltage V
OUT
can be determined by:
V
OUT
=V
CC
–(I
C2
+I
C6
)R2,(4)
where V
CC
=6V, R
2
=225
, I
C2
=8mA and I
C6
=5mA.
From here, it can be seen that the output voltage is approximately
3.1V to give relatively equal positive and negative output swings.
Diode Q
5
is included for bias purposes to allow direct coupling of
R
F2
to the base of Q
1
. The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (Q
6
and Q
2
) which increases
the DC bias voltage on the input stage (Q
1
) to a more desirable
value, and also increases the feedback loop gain. Resistor R
0
optimizes the output VSWR (Voltage Standing Wave Ratio).
Inductors L
1
and L
2
are bondwire and lead inductances which are
roughly 3nH. These improve the high-frequency impedance
matches at input and output by partially resonating with 0.5pF of pad
and package capacitance.
POWER DISSIPATION CONSIDERATIONS
When using the part at elevated temperature, the engineer should
consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the typical supply current is
25mA (32mA max). For operation at supply voltages other than 6V,
see Figure 3 for I
CC
versus V
CC
curves. The supply current is
inversely proportional to temperature and varies no more than 1mA
between 25
°
C and either temperature extreme. The change is 0.1%
per
°
C over the range.
The recommended operating temperature ranges are air-mount
specifications. Better heat-sinking benefits can be realized by
mounting the SO and N package bodies against the PC board
plane.
V
IN
L1
3nH
Q1
Q4
RF1
140
RE1
12
RF2
200
Q5
RE2
12
R3
140
Q6
10
3nH
L2
V
OUT
R2
225
V
CC
R1
650
R0
Q3
Q2
SR00209
Figure 17. Schematic Diagram
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