參數(shù)資料
型號： S9S08LG32J0VLK
廠商： Freescale Semiconductor
文件頁數(shù)： 17/50頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 32KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 90
系列： S08
核心處理器： S08
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LCD，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1.9K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 80-LQFP
包裝： 托盤
MC9S08LG32 Series Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor
24
Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power
2.9
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40
C to 105 C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
1 Data in Typical column was characterized at 5.0 V, 25
C or is typical recommended value.
Max
Unit
1
P
Average internal reference frequency — factory trimmed
at VDD = 5.0 V and temperature = 25
C
fint_ft
—
32.768
—
kHz
2
C
Average internal reference frequency — user trimmed
fint_t
31.25
—
39.0625
kHz
3
C
Internal reference start-up time
tIRST
—60
100
s
4
P
DCO output frequency range —
trimmed2
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
Low range (DRS = 00)
fdco_t
16
—
20
MHz
P
Mid range (DRS = 01)
32
—
40
5
P
DCO output frequency2
Reference = 32768 Hz
and
DMX32 = 1
Low range (DRS = 00)
fdco_DMX32
—
19.92
—
MHz
P
Mid range (DRS = 01)
—
39.85
—
6
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)3
3 This parameter is characterized and not tested on each device.
f
dco_res_t
—
0.1
0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)3
f
dco_res_t
—
0.2
0.4
%fdco
8
P
Total deviation of trimmed DCO output frequency over
voltage and temperature
f
dco_t
—–1.0
to +0.5
2%f
dco
9
C
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0
C to 70 C3
f
dco_t
—
0.5
1%f
dco
10
C
FLL acquisition time3, 4
4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
tAcquire
——
1
mS
11
C
Long term jitter of DCO output clock (averaged over 2 ms
interval)5
5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage
for a given interval.
CJitter
—0.02
0.2
%fdco
XOSC
EXTAL
XTAL
Crystal or Resonator
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