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參數(shù)資料
| 型號(hào)： | S9408P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Input, Quad 8-Bit Nonvolatile DACPOT |
| 中文描述： | 串行輸入，四路8位非易失DACPOT |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | S9408P |
4
S9408
2015 2.2 8/2/00
SUMMIT MICROELECTRONICS, Inc.
FIGURE 2. WRITE SEQUENCE
NONVOLATILE WRITE
A nonvolatile write is a two step operation: it is initiated by
taking CS# low and clocking in a start bit followed by the
NV Enable command. At this point the host can take CS#
back high or continue clocking in data. This data is don
’
t
care and will be ignored by the S9408. If any command
other than write follows NV enable the NV latch will be
cleared.
Next, the host takes CS# low again and issues a write
command and address and then clocks in the eight data
FIGURE 3. NONVOLATILE WRITE SEQUENCE
bits to be programmed. The host will then bring CS# HIGH
and the data will be latched into the data register and a
nonvolatile write operation will commence.
The status of the nonvolatile write can be monitored on the
RDY/BSY# pin. A logic low indicates the write is still in
progress and the S9408 will not be accessible to the host;
a logic high indicates the write has completed and the
S9408 is ready for the next command. Refer to Figure 3
for an illustration of the sequence of bus conditions for a
nonvolatile write operation.
S
T
A
R
T
C
D
A
C
D
A
1
0
3
4
5
6
7
1
1
2
0
0
D
D
D
D
D
D
CLK
DI
DO
Hi Z
VOUT
2015 T fig02 2.0
CS#
RDY/BSY#
(Pulled up to V
DD
)
A
0
1
D
CLK
DI
Rising Edge Sets
NV Write Enable Latch
C
C
1
0
C
C
1
0
D
A
D
A
1
0
3
4
5
6
7
1
2
0
D
D
D
D
D
D
Address and Data
are Don
’
t Care
Rising Edge Starts
NV Write
NV Write Enable
Latch is Reset
2015 T fig03 2.0
CS#
RDY/BSY#
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