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參數(shù)資料
| 型號： | S9408P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Input, Quad 8-Bit Nonvolatile DACPOT |
| 中文描述： | 串行輸入，四路8位非易失DACPOT |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 51K |
| 代理商： | S9408P |
2
S9408
2015 2.2 8/2/00
SUMMIT MICROELECTRONICS, Inc.
The analog outputs of the S9408 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256
th
of the voltage differential between V
REFH
and
V
REFL
of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition, each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9804 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V
REFL
and V
REFH
inputs sets the full-scale output voltage for its respective
DAC. V
REFL
must be equal to or greater than ground
(positive voltage). V
REFH
must be greater (more positive)
than V
REFL
and less than or equal to V
DD
.
PINOUT and SIGNAL DEFINITION
Pin
Name
Function
1, 2
20, 19
3
V
REFH
Vreference High:
V
REFL
< V
REFH
- V
DD
Power Supply Voltage
V
DD
4
RDY/BSY# Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5
CLK
Clock Input Pin: used for serial
data communication
Chip Select: When high deselects
the device and places it in a low
power mode
6
CS#
7
DI
Data Input: serial data input pin
8
9
DO
00/REG#
Data Output: serial data output pin
Power On Recall Option Input
10
GND
Power Supply Ground
11, 12
13, 14
V
REFL
Vreference Low:
V
REFH
> V
REFL
GND
15, 16
17, 18
V
OUT
DAC Output: buffered D to A
converter output
Output Buffer Amplifiers
The voltage outputs are precision unity-gain followers that
slew up to 1V/μs. The outputs can swing from V
REFL
to
V
REFH
. With a 0V to 5V output transition the amplifier
outputs typically settle to 1LSB in 40μs.
DIGITAL INTERFACE
The S9408 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data In
(DI) and Data Out (DO). Data is clocked into the device on
the clock
’
s rising edge and out of the device on the clock
’
s
falling edge. Data is shifted in and out MSB first. DO only
becomes active after the device has been selected and
after a valid read command and address has been re-
ceived.
All data transfers are initiated after CS# goes low and a
logic
‘
1
’
is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
VREFH1
VREFH0
VDD
RDY/BSY#
CLK
CS#
DI
DO
00/REG#
GND
VREFH2
VREFH3
VOUT0
VOUT1
VOUT2
VOUT3
VREFL3
VREFL2
VREFL1
VREFL0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
2015 T PCon 2.0
20-Pin PDIP
or 20-Pin SOIC
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