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參數(shù)資料
| 型號： | S80C52XXX-36SHXXX:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 7004K |
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148
7593L–AVR–09/12
AT90USB64/128
Figure 16-3. Output Compare unit, block diagram.
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR2x directly.
16.4.1
Force output compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the
OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or
toggled).
16.4.2
Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-
ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
16.4.3
Using the Output Compare unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
OCFnx (int.req.)
= (8-bit comparator)
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform generator
top
FOCn
COMnX1:0
bottom
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相關代理商/技術參數(shù) |
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| S80C54 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
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| S80C54-2 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| S80C54-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| S80C54-24 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
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