
201
ATmega8A [DATASHEET]
8159E–AVR–02/2013
24.8.7
Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM
within four clock cycles after writing SPMCR. The only accessible Lock Bits are the Boot Lock Bits that may pre-
vent the Application and Boot Loader section from any software update by the MCU.
See
Table 24-2 and
Table 24-3 for how the different settings of the Boot Loader Bits affect the Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is
executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is don’t care during this
operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for read-
ing the Lock Bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing
the Lock Bits. When programming the Lock Bits the entire Flash can be read during the operation.
24.8.8
EEPROM Write Prevents Writing to SPMCR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
Bits from software will also be prevented during the EEPROM write operation. It is recommended that the user
checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCR
Register.
24.8.9
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the Z-pointer with
0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three CPU
cycles after the BLBSET and SPMEN bits are set in SPMCR, the value of the Lock Bits will be loaded in the desti-
nation register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock Bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When
BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits. To read
the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of
the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to
Table 25-4 on page 209for a detailed description and mapping of the fuse low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits (FHB)
will be loaded in the destination register as shown below. Refer to
Table 25-3 on page 208 for detailed description
and mapping of the fuse high bits.
Fuse and Lock Bits that are programmed, will be read as zero. Fuse and Lock Bits that are unprogrammed, will be
read as one.
Bit
7
6543210
R0
1
BLB12
BLB11
BLB02
BLB01
1
Bit
76543210
Rd
–
BLB12
BLB11
BLB02
BLB01
LB2
LB1
Bit
7
65
4
3
210
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
765
4
3210
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0