
iii
LIST OF FIGURES
PAGE
Figure 1
The 80960SB Processor’s Highly Parallel Architecture ................................................................ 0
Figure 2
80960SB Programming Environment ........................................................................................... 1
Figure 3
Instruction Formats ...................................................................................................................... 4
Figure 4
Multiple Register Sets Are Stored On-Chip .................................................................................. 6
Figure 5
Connection Recommendation for LOCK .................................................................................... 11
Figure 6
Typical Supply Current vs. Case Temperature ........................................................................... 12
Figure 7
Typical Current vs. Frequency (Room Temp) ............................................................................. 12
Figure 8
Typical Current vs. Frequency (Hot Temp) ................................................................................. 13
Figure 9
Capacitive Derating Curve ......................................................................................................... 13
Figure 10
Test Load Circuit for Three-State Output Pins ............................................................................ 13
Figure 11
Drive Levels and Timing Relationships for 80960SB Signals ..................................................... 15
Figure 12
Processor Clock Pulse (CLK2) ................................................................................................... 18
Figure 13
RESET Signal Timing ................................................................................................................. 18
Figure 14
HOLD Timing .............................................................................................................................. 19
Figure 15
80-Lead EIAJ Quad Flat Pack (QFP) Package .......................................................................... 20
Figure 16
84-Lead Plastic Leaded Chip Carrier (PLCC) Package ............................................................. 21
Figure 17
Non-Burst Read and Write Transactions Without Wait States .................................................... 27
Figure 18
Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States ................................ 28
Figure 19
Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred) .............................. 29
Figure 20
Accesses Generated by Quad Word Read Bus Request,
Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States
30
Figure 21
Interrupt Acknowledge Cycle ...................................................................................................... 31
Figure 22
Cold Reset Waveform ................................................................................................................ 32
LIST OF TABLES
Table 1
80960SB Instruction Set .............................................................................................................. 3
Table 2
Memory Addressing Modes ......................................................................................................... 4
Table 3
Sample Floating-Point Execution Times (
s) at 16 MHz ..............................................................6
Table 4
80960SB Pin Description: Bus Signals ........................................................................................ 8
Table 5
80960SB Pin Description: Support Signals ................................................................................ 10
Table 6
DC Characteristics ..................................................................................................................... 14
Table 7
80960SB AC Characteristics (10 MHz) ...................................................................................... 16
Table 8
80960SB AC Characteristics (16 MHz) ...................................................................................... 17
Table 9
80960SB QFP Pinout — In Pin Order ........................................................................................ 22
Table 10
80960SB QFP Pinout — In Signal Order ................................................................................... 23
Table 11
80960SB PLCC Pinout — In Pin Order ...................................................................................... 24
Table 12
80960SB PLCC Pinout — In Signal Order ................................................................................. 25
Table 13
80960SB QFP Package Thermal Characteristics ...................................................................... 26
Table 14
80960SB PLCC Package Thermal Characteristics .................................................................... 26