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參數(shù)資料
| 型號(hào)： | S80296SA40 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | S80296SA40 |
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PRELIMINARY
25
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
T
WHBX
BHE#, INST Hold after WR# Rising Edge
0
ns
T
WHAX
A19:0, CS
x# Hold after WR# Rising Edge
0
ns
T
RHBX
BHE#, INST Hold after RD# Rising Edge
0
ns
T
RHAX
A19:0, CS
x# Hold after RD# Rising Edge
0
Table 11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode
Symbol
Parameter
Min
Max
Units
T
AVDV
A19:0 Valid to Input Data Valid
4t – 28
ns (1, 2, 3)
T
RLDV
RD# Active to Input Data Valid
3t – 25
ns (1, 2)
T
SLDV
Chip Select Low to Data Valid
4t – 28
ns (1, 2, 3)
T
CHDV
CLKOUT High to Input Data Valid
2t – 25
ns
T
RHDZ
End of RD# to Input Data Float
t
ns (2, 3)
T
RXDX
Data Hold after RD# Inactive
0
ns
T
AVYV
A19:0 Valid to READY Setup
3t – 45
ns (4)
T
CH
1YX
First READY Hold (active) after CLKOUT High
t – 4
2t – 21
ns (5, 6)
T
CH
2YX
Non-first READY Hold (active) after CLKOUT High
0
2t – 21
ns (5)
T
YLYH
Non READY (inactive) Time
2t
No Upper
Limit
ns
NOTES:
1.
If using the READY signal to insert wait states, you must program at least one wait state in the
BUSCON
x register because the first falling edge of READY is not synchronized with a CLKOUT edge.
2.
If using the BUSCON
x register without the READY signal to insert wait states, add 2t
× n, where n =
number of wait states.
3.
If CS
x# changes or if a write cycle follows a read cycle, add 2t (1 state).
4.
If using the BUSCON
x register to insert wait states, add (2t
× n–1), where n = number of wait states.
5.
Exceeding the maximum specification causes additional wait states.
6.
If you program two or more wait states in the BUSCON
x register, the T
CH
1YX minimum does not apply.
Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode (Continued)
Symbol
Parameter
Min
Max
Units
NOTES:
1.
25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2.
When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3.
If using either READY or BUSCON
x to insert wait states, add 2t
× n, where n = number of wait states.
4.
Assuming back-to-back bus cycles.
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