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參數(shù)資料
| 型號： | S80296SA40 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 2/40頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | S80296SA40 |
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6
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0
SIGNALS
Table 4. Signal Descriptions
Name
Type
Description
A15:0
I/O
System Address Bus
These address pins provide address bits 0–15 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes.
A19:16
I/O
Address Pins 16–19
These address pins provide address bits 16–19 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes, supporting extended
addressing of the 1-Mbyte address space.
NOTE:
Internally, there are 24 address bits; however, only 20 external address
pins (A19:0) are implemented. The internal address space is 16 Mbytes
(000000–FFFFFFH) and the external address space is 1 Mbyte (00000–
FFFFFH). The microcontroller resets to FF2080H.
A19:16 share package pins with EPORT.3:0.
AD15:0
I/O
Address/Data Lines
These pins provide a multiplexed address and data bus. During the address phase
of the bus cycle, address bits 0–15 are presented on the bus and can be latched
using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred.
AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles. ALE
signals the start of an external bus cycle and indicates that valid address information
is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed
bus; A19:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
BHE#
O
Byte High Enable
During 16-bit bus cycles, this active-low output signal is asserted for word and high-
byte reads and writes to external memory. BHE# indicates that valid data is being
transferred over the upper half of the system data bus. Use BHE#, in conjunction
with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed
address/data bus), to determine which memory byte is being transferred over the
system bus:
BHE#
AD0 or A0
Byte(s) Accessed
0
both bytes
0
1
high byte only
1
0
low byte only
BHE# shares a package pin with WRH#.
Chip configuration register 0 (CCR0) determines whether this pin functions as
BHE# or as WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
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