- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365451 > S71WS512N80BAIZZ0 (Spansion Inc.) Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt PDF資料下載
參數(shù)資料
| 型號： | S71WS512N80BAIZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 26/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAIZZ0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
26
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while program-
ming or erasing in another bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank
(except the sector being erased).
Figure 31
shows how read and write cycles may
be initiated for simultaneous operation with zero latency. Refer to the DC Char-
acteristics table for read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous
write operation. While the device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is ignored when the device is
configured in the Asynchronous mode. When in the Synchronous read mode con-
figuration, the device is able to perform both Asynchronous and Synchronous
write operations. CLK and AVD# induced address latches are supported in the
Synchronous programming mode. During a synchronous write operation, to write
a command or command sequence (which includes programming data to the de-
vice and erasing sectors of memory), the system must drive AVD# and CE# to
V
IL
, and OE# to V
IH
when providing an address to the device, and drive WE# and
CE# to V
IL
, and OE# to V
IH
when writing commands or data. During an asyn-
chronous write operation, the system must drive CE# and WE# to V
IL
and OE#
to V
IH
when providing an address, command, and data. Addresses are latched
on the last falling edge of WE# or CE#, while data is latched on the 1st rising
edge of WE# or CE# (see
Table 16
).
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 12
indicates the address space that each sector occupies. The device ad-
dress space is divided into sixteen banks: Banks 1 through 14 contain only 64
Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in ad-
dition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits re-
quired to uniquely select a sector.
I
CC2
in
“DC Characteristics”
represents the active current specification for the
write mode.
“AC Characteristics—Synchronous”
and
“AC Characteristics—Asyn-
chronous”
contain timing specification tables and timing diagrams for write
operations.
Unlock Bypass Mode
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a set of words, instead of four. See the "
Unlock Bypass
Command Sequence
" section for more details.
Accelerated Program/Erase Operations
The device offers accelerated program and accelerated chiperase operations
through the ACC function. ACC is intended to allow faster manufacturing
throughput at the factory and not to be used in system operations.
If the system asserts V
HH
on this input, the device automatically enters the
aforementioned Unlock Bypass mode and uses the higher voltage on the input to
reduce the time required for program and erase operations. The system can then
use the Write Buffer Load command sequence provided by the Unlock Bypass
mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in Unlock By-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71WS512N80BAIZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。