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參數(shù)資料
| 型號： | S71WS512N80BAIZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 24/142頁 |
| 文件大小： | 1996K |
| 代理商： | S71WS512N80BAIZZ0 |
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24
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst read and linear burst read
of a preset length. When the device first powers up, it is enabled for asynchro-
nous read operation.
Prior to entering burst mode, the system should determine how many wait states
are desired for the initial word (t
IACC
) of each burst access, what mode of burst
operation is desired, which edge of the clock will be the active clock edge, and
how the RDY signal will transition with valid data. The system would then write
the configuration register command sequence. See "
Set Configuration Register
Command Sequence
" section for further details.
Once the system has written the “Set Configuration Register” command se-
quence, the device is enabled for synchronous reads only.
The initial word is output t
IACC
after the active edge of the first CLK cycle. Sub-
sequent words are output t
BACC
after the active edge of each successive clock
cycle at which point the internal address counter is automatically incremented.
Note that the device has a fixed internal address boundary that occurs every 128
words, starting at address 00007Fh. No boundary crossing latency is required
when the device operates at or below 66 MHz to reach address 000080h. When
the device operates above 66 MHz, a boundary crossing of one additional wait
state is required. The timing diagram can be found in
Figure 28
.
When the starting burst address is not divisible by four, additional waits are re-
quired. For example, if the starting burst address is divisible by four A1:0 = 00,
no additional wait state is required, but if the starting burst address is at address
A1:0 = 01, 10, or 11, one, two or three wait states are required, respectively,
until data DQ4 is read. The RDY output indicates this condition to the system by
deasserting (see
Table 3
and
Table 13
).
Continuous Burst
The device will continue to output sequential burst data, wrapping around to ad-
dress 000000h after it reaches the highest addressable memory location, until
the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See
Table 2
.
If the host system crosses a bank boundary while reading in burst mode, and the
subsequent bank is not programming or erasing, a one-cycle latency is required
as described above if the device is operating above 66 MHz. If the device is op-
erating at or below 66 MHz, no boundary crossing latency is required. If the host
system crosses the bank boundary while the subsequent bank is programming or
erasing, the device will provide read status information. The clock will be ignored.
After the host has completed status reads, or the device has completed the pro-
gram or erase operation, the host can restart a burst operation using a new
address and AVD# pulse.
Table 3. Address Dependent Additional Latency
Initial
Address
A[10]
00
01
10
11
Cycle
X
X+1
DQ1
DQ2
D
Q
3
X+2
DQ2
D
Q
3
X+3
D
Q
3
X+4
DQ4
DQ4
DQ4
DQ4
X+5
DQ5
DQ5
DQ5
DQ5
X+6
DQ6
DQ6
DQ6
DQ6
DQ0
DQ1
DQ2
D
Q
3
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| S71WS512N80BAIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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