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參數(shù)資料
| 型號(hào)： | S71PL032JA0BFW0F4 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁數(shù)： | 106/188頁 |
| 文件大?。?/td> | 5078K |
| 代理商： | S71PL032JA0BFW0F4 |
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May 21, 2004 S29PL127_064_032J_00_A1
S29PL127J/S29PL064J/S29PL032J for MCP
23
Prelimin ary
General Description
The PL127J/PL064J/PL032J is a 128/128/64/32Mbit, 3.0 volt-only Page Mode and
Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords.
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V VPP is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding ran-
dom access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Bank
PL127J Sectors
PL064J Sectors
PL032J Sectors
A
16Mbit (4 Kw x 8 and 32 Kw x 31)
8Mbit (4 Kw x 8 and 32 Kw x 15)
4Mbit (4 Kw x 8 and 32 Kw x 7)
B
48Mbit (32 Kw x 96)
24Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
C
48Mbit (32 Kw x 96)
24Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
D
16Mbit (4 Kw x 8 and 32 Kw x 31)
8Mbit (4 Kw x 8 and 32 Kw x 15)
4Mbit (4 Kw x 8 and 32 Kw x 7)
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相關(guān)代理商/技術(shù)參數(shù) |
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| S71PL032JA0BFW0Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW0Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW0Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW9Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
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