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參數(shù)資料
| 型號(hào)： | S71PL032JA0BFW0F4 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁(yè)數(shù)： | 104/188頁(yè) |
| 文件大?。?/td> | 5078K |
| 代理商： | S71PL032JA0BFW0F4 |
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Publication Number S29PL127_064_032J_00_
Revision A Amendment 1 Issue Date May 21, 2004
PRELIMINARY
S29PL127J/S29PL064J/S29PL032J for
MCP
128/128/64/32 Megabit (8/4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIOTM Control
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/64/32Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
— 4 separate banks, with up to two simultaneous
operations per device
—Bank A:
PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7)
—Bank B:
PL127J - 48Mbit (32 Kw x 96)
PL064J - 24Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
—Bank C:
PL127J - 48Mbit (32 Kw x 96)
PL064J - 24Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
—Bank D:
PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7)
Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the VIO pin
—VIO options at 1.8 V and 3 V I/O for PL127J devices
—3V VIO for PL064J and PL032J devices
SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 A typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV, Am29DL,
and AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL032JA0BFW0Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW0Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW0Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW9Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032JA0BFW9Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
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