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參數(shù)資料
| 型號(hào)： | S71AL016D02BAWTF2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁數(shù)： | 73/76頁 |
| 文件大?。?/td> | 909K |
| 代理商： | S71AL016D02BAWTF2 |
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August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
73
P r e l i m i n a r y
Notes:
1. The internal write time of the memory is defined by the overlap of WE#, CE# = V
IL
, BHE# and/or BLE# = V
IL
. All signals
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
2. Data I/O is high-impedance if OE# = V
IH
.
3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
4. During this period, the I/Os are in output state and input signals should not be applied.
Notes:
1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
2. During this period, the I/Os are in output state and input signals should not be applied.
Figure 6. Write Cycle 2 (CE# Controlled)
Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW)
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE#
ADDRESS
WE#
DATA I/O
OE#
NOTE4
t
BW
t
SA
BHE#/BLE#
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE#
ADDRESS
WE#
DATAI/O
NOTE 2
t
BW
BHE#/BLE#
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