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參數資料
| 型號： | S71AL016D02BAWBF0 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁數： | 30/76頁 |
| 文件大?。?/td> | 909K |
| 代理商： | S71AL016D02BAWBF0 |
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S29AL016D
S29AL016D_00_A1_E August 4, 2004
A d v a n c e I n f o r m a t i o n
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a
hardware reset
during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See “Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 4
illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in “AC Characteristics” for parameters, and to
Figure 18
for tim-
ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Table
9
shows the address and data re-
quirements for the sector erase command sequence.
The device does
not
require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 μs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 μs, the system need not monitor DQ3.
Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data.
The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. Note that a
hardware reset
during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to
“Write Operation Status” for information on these status bits.)
Figure 4
illustrates the algorithm for the erase operation. Refer to the Erase/Pro-
gram Operations tables in the “AC Characteristics” section for parameters, and to
Figure 18
for timing diagrams.
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