參數(shù)資料
    型號(hào): S70WS512N00BAWAB2
    廠商: Spansion Inc.
    英文描述: Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
    中文描述: 同硅晶片堆疊多芯片產(chǎn)品(MCP)的512兆位(32兆× 16位)的CMOS 1.8伏,只有同時(shí)讀/寫,突發(fā)模式閃存
    文件頁數(shù): 27/93頁
    文件大?。?/td> 846K
    代理商: S70WS512N00BAWAB2
    28
    S70WS512N00 Based MCPs
    S70WS512N00_00_A0 March 14, 2005
    A d v a n c e I n f o r m a t i o n
    Reading the Configuration Table.
    The configuration register can be read with a four-cycle com-
    mand sequence. See
    Table 13.1
    for sequence details. Once the data has been read from the
    configuration register, a software reset command is required to set the device into the correct
    state.
    8.4
    Autoselect
    The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-
    tion. This mode is primarily intended for programming equipment to automatically match a device
    with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-
    tem. When verifying sector protection, the sector address must appear on the appropriate highest
    order address bits (see
    Table 8.9
    ). The remaining address bits are don't care. The most significant
    four bits of the address during the third write cycle selects the bank from which the Autoselect
    codes are read by the host. All other banks can be accessed normally for data read without exiting
    the Autoselect mode.
    To access the Autoselect codes, the host system must issue the Autoselect command.
    Table 8.8 Configuration Register
    CR Bit
    Function
    Settings (Binary)
    CR15
    Set Device Read
    Mode
    0 = Synchronous Read (Burst Mode) Enabled
    1 = Asynchronous Read Mode (default) Enabled
    CR14
    Boundary Crossing
    54 MHz
    66 Mhz
    80 MHz
    S29WS064N
    S29WS128N
    N/A
    N/A
    N/A
    Default value is
    0
    S29WS256N
    0
    1
    1
    0 = No extra boundary crossing latency
    1 = With extra boundary crossing latency (default)
    Must be set to
    1
    greater than 54 MHz.
    CR13
    Programmable
    Wait State
    S29WS064N
    S29WS128N
    0
    1
    1
    011 = Data valid on 5th active CLK
    edge after addresses latched
    100 = Data valid on 6th active CLK
    edge after addresses latched
    101 = Data valid on 7th active CLK
    edge after addresses latched (default)
    110 = Reserved
    111 = Reserved
    Inserts wait states before initial data
    is available. Setting greater number of wait
    states before initial data reduces latency
    after initial data. (Notes
    1
    ,
    2
    )
    S29WS256N
    CR12
    S29WS064N
    S29WS128N
    1
    0
    0
    S29WS256N
    CR11
    S29WS064N
    S29WS128N
    1
    0
    1
    S29WS256N
    CR10
    RDY Polarity
    0 = RDY signal active low
    1 = RDY signal active high (default)
    CR9
    Reserved
    1 = default
    CR8
    RDY
    0 = RDY active one clock cycle before data
    1 = RDY active with data (default)
    When CR13-CR11 are set to 000,
    RDY is active with data regardless of CR8 setting.
    CR7
    Reserved
    1 = default
    CR6
    Reserved
    1 = default
    CR5
    Reserved
    0 = default
    CR4
    Reserved
    0 = default
    CR3
    Burst Wrap Around
    0 = No Wrap Around Burst
    1 = Wrap Around Burst (default)
    CR2
    CR1
    CR0
    Burst Length
    000 = Continuous (default)
    010 = 8-Word Linear Burst
    011 = 16-Word Linear Burst
    100 = 32-Word Linear Burst
    (All other bit settings are reserved)
    Notes:
    1.
    2.
    3.
    Refer to
    Tables
    8.2
    -
    8.6
    for wait states requirements.
    Refer to Synchronous Burst Read timing diagrams
    Configuration Register is in the default state upon power-up or hardware reset.
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