參數(shù)資料
型號： S6B0759
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
中文描述： 81的COM / 128賽格驅(qū)動
文件頁數(shù)： 13/68頁
文件大?。?/td> 657K
代理商： S6B0759
S6B0759 PRELIMINARY SPEC. VER. 1.2
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
9
MICROPROCESSOR INTERFACE
Table 5. Microprocessor Interface Pins
Name
I/O
Description
RESETB
I
Reset the input pin
When RESETB is "L", initialization is executed.
Parallel/Serial data input select input
PS0
Interface
Mode
Data/
Instruction
Data
Read / Write
Serial Clock
H
Parallel
RS
DB0 to DB7
E_RD
RW_WR
Write only
-
L
Serial
RS or None
SID(DB7)
SCLK(DB6)
PS0
I
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR
must be fixed to either "H" or "L".
Microprocessor interface select input pin
PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface
PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface
PS0 = “L” , PS1 = "H": 4 Pin-SPI serial MPU interface
PS0 = “L” , PS1 = "L": 3 Pin-SPI serial MPU interface
Chip select input pins
Data/instruction I/O is enabled only when CS1B is "L" . When chip select is non-active, DB0
to DB7 may be high impedance.
Register select input pin
RS = "H": DB0 to DB7 are display data
RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
PS1
MPU Type
RW_WR
Read/Write control input pin
RW = "H": read
RW = "L": write
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
PS1
I
CS1B
I
RS
I
Description
H
6800-series
RW
L
8080-series
/WR
RW_WR
I
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