- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365429 > S5T8808 (SAMSUNG SEMICONDUCTOR CO. LTD.) PLL FREQUENCY SHNTHESIZER FOR PAGER PDF資料下載
參數(shù)資料
| 型號： | S5T8808 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PLL FREQUENCY SHNTHESIZER FOR PAGER |
| 中文描述： | 鎖相環(huán)頻率SHNTHESIZER的尋呼機(jī) |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 93K |
| 代理商： | S5T8808 |
S5T8808
PLL FREQUENCY SHNTHESIZER FOR PAGE
4
PIN DESCRIPTION
Pin No
Symbol
I/O
Description
1
OSCI
I
These input / output pins generate the reference frequency.
In case of an OSCI pin, external reference frequency can be input through an AC
coupling.
2
OSCO
O
3
V
DD3
The highest potential supply terminal that can be supplied up to 2.0V ~ 3.3V,
except for V
DD1
and V
DD2
.
The Output of RX Phase detector terminal for active loop filter.
There are 3-kinds of output signal states according to Rx Loop Error
If Fr < Fn (Fr is leading), the output negative pulse state
If Fr > Fn (Fr is lagging), the output positive pulse state
If Fr = Fn (the same phase), the output is high impedance state
4
PDA
O
5
PDP
O
The Output of RX Phase detector terminal for active loop filter.
There are 3-kinds of output signal states according to Rx Loop Error
If Fr < Fn (Fr is lagging), the output negative pulse state
If Fr > Fn (Fr is leading), the output positive pulse state
If Fr = Fn (the same phase), the output is high impedance state
6
V
SS
Fin
Ground terminal
7
I
Input terminal for 16-bit Divider from VCO.
Mostly, VCO output should be input through an AC coupling and the minimum
input level is 500mV
P-P
(in case of 90MHz)
Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up
to 0.95 ~ 2.0V from V
SS
.
Voltage supply terminal for each Divider block (N & R counter).
This pin can be supplied up to 0.95V ~ 2.0V.
8
V
DD1
I
9
V
DD2
I
10
LDT
O
Lock detector is also an output of the Phase Detector.
The Low state of this output shows the unlock status, which is the error width
between the Ref. signal and the VCO output signal.
11
CLK
I
These pins are controlled by
μ
-controller and it also has Schmitt Trigger
architecture.
The features of these pins are as follows; Clock input for 17-bit Shift Register,
Serial data input (it include FnFr-on / off and FRC),
Latch enable input (User selectable EN1 or EN2)
12
DATA
I
13
EN
I
14
Fn
O
Output terminal for divider value of N-counter. To control the output On/Off, the
FnFr bit of the Reference register can be programmed.
When FnFr bit set to High, this output shows low level.
15
Fr
O
Output terminal for divider value of N-counter. To control the output On/Off, the
FnFr bit of Reference register can be programmed.
When FnFr bit set to High, this output shows low level.
16
NC
No Connection. (Internally biased Pull-up)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5T8809X01-R0B0 | RF Coaxial Connector Adapter; Convert From:Jack; Convert To:Plug; Body Style:Right Angle Adapter, Plug-Jack; Impedance:50ohm; Contact Termination:Crimp RoHS Compliant: Yes |
| S5T8809 | PLL FREQUENCY SYNTHESIZER FOR PAGER |
| S5X713CX03 | 1/7 OPTICAL SIZE 352x288(CIF) CAMERA MODULE |
| S5X713CX03-20R0-40AJAA | 1/7 OPTICAL SIZE 352x288(CIF) CAMERA MODULE |
| S6A0073 | 34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5T8808A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PLL FREQUENCY SHNTHESIZER FOR PAGER |
| S5T8808A01-R0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PLL FREQUENCY SHNTHESIZER FOR PAGER |
| S5T8808X01-V0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PLL FREQUENCY SHNTHESIZER FOR PAGER |
| S5T8809 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER FOR PAGER |
| S5T8809X01-R0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER FOR PAGER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。