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參數(shù)資料
| 型號： | S5T8809 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PLL FREQUENCY SYNTHESIZER FOR PAGER |
| 中文描述： | 鎖相環(huán)頻率合成器的尋呼機 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 123K |
| 代理商： | S5T8809 |
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
1
INTRODUCTION
S5T8809 is a superior low-power-programmable PLL frequency
synthesizer which can be used in high performance / Simple
application for a Wide Area Pager system.
S5T8809 consists of 2 kinds of divider block including a 19-bit Shift
register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit N-
Counter, 32/33 Prescaler, and a phase detector block including a
Phase detector, Lock detector and a Charge pump.
S5T8809 also has a battery saving mode which can control each
register block by serial control data from the
μ
-controller (MICOM)
and it also has boost up signal output for fast locking.
FEATURES
Maximum operating frequency: 330MHz @ 300mV
P-P
, V
DD1
= 1.0V, V
DD2
= 3.0V
On-chip reference oscillator supports external crystal which oscillates up to 23MHz
Superior supply current:
— F
FIN
= 310MHz, I
DD1
= 0.8mA (Typ.) @ V
DD1
= 1.0V, V
DD2
= 3.0V
Operating voltage: V
DD1
= 0.95 to 1.5V and V
DD2
= 2.0 to 3.3V
Excellent Divider range:
— Ref. Divider:
FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default
FRC (1): 1 / 5 to 1 / 32767
— Rx Divider:
PBC (0): 1 / 1056 ~ 1 / 65535: Default
PBC (1): 1 / 1056 ~ 1 / 262143
Boost-up signal output for Fast Locking
In the Standby mode, VDD1 block can be controlled by BSB Pin status
— Standby current consumption: 10
μ
A (Max.)
Programmable control the output of LD to reduce internal noise
Programmable 17 / 19-bit shift register value controlled by PBC
Charge pump output circuitry for passive filter
Package type: 16
TSSOP (0.65mm)
ORDERING INFORMATION
+: New Product
Device
Package
Operating Temperature
+S5T8809X01-R0B0
16
TSSOP
0044
25
°
C to +75
°
C
16-TSSOP-0044
( Magnification = 1 : 4 )
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