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參數(shù)資料
| 型號： | S4402 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PLL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS鎖相環(huán)時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PLL時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝鎖相環(huán)時鐘發(fā)生器） |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 154K |
| 代理商： | S4402 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 10
BOARD LAYOUT CONSIDERATIONS
The S4402/S4403 chips are sensitive to noise on
the Analog +5 V and Filter pins. Care should be
taken during board layout for optimum results.
All decoupling capacitors (C1–C4 = 0.1
μ
F) should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4402/S4403 and the power and ground plane con-
nections.
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Figure 6. Board Layout (S4402 shown)
Component
Description
C1–C4
0.1
μ
F ceramic capacitor
C6
0.1
μ
F ceramic capacitor
R1
1.5 K 10% resistor
FB1,FB2
Ferrite bead or inductor
No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 6) to avoid the possibility of noise due
to crosstalk.
The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
The analog VCC plane should be separated from
the digital VCC and ground planes by at least 1/8
inch.
C1
1
2
3
4
5
6
7
8
9
10
1112
13 14 15 16 17 18
19
20
21
22
23
24
25
27
28
GND
D
C6
FB1
C3
C2
+5
D
C4
+5
A
+5
D
+5
D
R1
26
No signals should pass through
the area enclosed by dashed lines
FB2
A GND
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| S-4406-DB | 制造商:Molex 功能描述: |
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