
Chapter 24 Analog-to-Digital Converter (ADC12B16C) Block Description
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
1087
24.3.2.8
ATD Compare Enable Register (ATDCMPE)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
3–0
CC[3:0]
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If
in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counters wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
Module Base + 0x0008
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CMPE[15:0]
W
Reset
0
0000000
Figure 24-10. ATD Compare Enable Register (ATDCMPE)
Table 24-17. ATDCMPE Field Descriptions
Field
Description
15–0
CMPE[15:0]
Compare Enable for Conversion Number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence
— These bits enable automatic compare of conversion results individually for conversions of a sequence. The
sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will ag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
Table 24-16. ATDSTAT0 Field Descriptions (continued)
Field
Description