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參數(shù)資料
| 型號： | S3F49FAXZZ |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3F49FAX for Compact Flash SPECIFICATION Revision 1.0 |
| 中文描述： | S3F49FAX的閃存規(guī)范修訂版1.0 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 296K |
| 代理商： | S3F49FAXZZ |
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SPECIFICATION
S3F49FAX
12
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
100-Pin Number
I/O
Description
XREG
76
I
ATTRIBUTE MEMORY AREA SELECTION:
This signal is used during memory cycles to distinguish
between common memory and register (Attribute) memory
accesses. High for Common memory, low for attribute
memory.
The signal must also be active (low) during I/O cycles when
the I/O address is on the Bus.
In True IDE mode, this input signal is not used and should be
connected to VCC by the host.
XCE1
XCE2
99
98
I
CARD ENABLE:
These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is
being performed.
-CE2 always accesses the odd byte of the word.
-CE1 accesses the even byte or the Odd byte of the
word depending on A0 and -CE2. A multi-plexing
scheme based on A0, -CE1, -CE2 allows 8 bit hosts
to access all data on XDB0-XDB7.
This signal is the same as the PC card memory mode signal
in PC Card I/O mode.In the True IDE mode, CS0 is the chip
select for the task file registers while CS1 is used to select
the alternate status register and the device control register.
XOE
96
I
OUTPUT ENABLE:
This is an output enable strobe generated by the host
interface. It is used to read data from the PC Card in memory
mode and to read the CIS and configuration registers.
In PC Card I/O mode, this signal is used to read the CIS and
configuration registers. To enable True IDE mode this input
should be grounded by the host.
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