
CONTROL REGISTERS
S3C8639/C863A/P863A/C8647/F8647
4-12
DCSR0 —
DDC Control/Status Register 0
ECH Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
–
.0
0
RESET
Value
Read/Write
Addressing Mode
R/W
Register addressing mode only
R/W
R/W
R/W
R
R
–
R
.7–.6
Master/Slave, Tx/Rx Mode Selection Bits
0
0
Slave receiver mode (Default mode)
0
1
Slave transmitter mode
1
0
Master receiver mode
1
1
Master transmitter mode
.5
Bus Busy Bit
0
IIC-bus is not busy (when read), stop condition generation (when write)
1
IIC-bus is busy (when read), start condition generation (when write)
.4
DDC Module Enable Bit
0
Disable DDC module
1
Enable DDC module
.3
Arbitration Lost Bit
0
Bus arbitration status okay
1
Bus arbitration failed during serial I/O
.2
DDC Address/Data classification Bit
0
When reset or start/stop condition is generated, or when the received data is
in the data field.
1
When the received slave address matchs to DAR0, DAR1 register
.1
Not used for the S3C8639/C863A/C8647
.0
Received Acknowledgement (ACK) Bit
0
ACK is received
1
ACK is not received
NOTE:
Bits 3–0 are read only.