
RESET
and POWER-DOWN
S3C8639/C863A/P863A/C8647/F8647
8-4
Table 8-2. Set 1, Bank 0 Register Values after Reset (Continued)
Register Name
Mnemonic
Address
Dec
241
242
243
244
245
246
247
248
Bit Values After Reset
5
4
–
–
0
0
–
–
0
0
0
0
1
1
0
0
x
x
Hex
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
7
–
0
–
0
0
1
–
x
6
–
0
–
0
0
1
0
x
3
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer M1 counter register high
Timer M1 counter register low
Timer M1 data register high
Timer M1 data register low
Timer M1 control register
Timer M2 control register
A/D converter control register
A/D converter data register
TM1CNTH
TM1CNTL
TM1DATAH
TM1DATAL
TM1CON
TM2CON
ADCON
ADDATA
x
(4)
0
0
0
x
(4)
0
0
0
x
(4)
1
1
0
x
(4)
1
1
0
Pseudo Hsync generation register
Pseudo Vsync generation register
Stop control register
PHGEN
PVGEN
STOPCON
Location FCH is not mapped.
BTCNT
EMT
IPR
249
250
251
F9H
FAH
FBH
0
0
0
1
1
0
0
0
0
1
1
0
Basic timer counter register
External memory timing register
Interrupt priority register
253
254
255
FDH
FEH
FFH
0
0
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
0
x
0
–
x
NOTES:
1.
Except for SYNCRD, TM1CNTH, TM1CNTL, TM1DATAH, TM1DATAL, ADDATA, and BTCNT, all registers in set 1,
bank 0 are read/write addressable.
You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB. The read-only
registers in the S3C8639/C863A/C8647 register file are: TM0CNT, TM0DATA, IRQ, SYNCRD, TM1CNTH, TM1CNTL,
TM1DATAH, TM1DATAL, ADDATA, BTCNT, PWMCNT, and RBDR.
Interrupt pending flags that must be cleared by software are noted by shaded table cells.
Not mapped for the S3C8647.
2.
3.
4.