參數(shù)資料
型號(hào): S3C7559XX-QT
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 20 MM, QFP-64
文件頁(yè)數(shù): 56/197頁(yè)
文件大?。?/td> 1181K
代理商: S3C7559XX-QT
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TIMERS and TIMER/COUNTERS
S3C7559/P7559
11-20
TC REFERENCE REGISTER (TREFn)
The TC reference register TREFn is an 8-bit write-only register that is
RESET initializes the TREFn value to
'FFH'.
TREFn is used to store a reference value to be compared to the incrementing TCNTn register in order to identify
an elapsed time interval. Reference values will differ depending upon the specific function that TC is being used
to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output
source.
During timer/counter operation, the value loaded into the reference register is compared to the counter value.
When TCNTn = TREFn, the TC output latch (TOLn) is inverted and an interrupt request is generated to signal the
interval or event. The TREFn value, together with the TMODn clock frequency selection, determines the specific
TC timer interval. Use the following formula to calculate the correct value to load to the TREFn reference
register:
TC timer interval = (TREFn value + 1)
×
1
TMODn frequency setting
( assuming a TREFn value
≠ 0 )
TC OUTPUT ENABLE FLAG (TOEn)
The 1-bit timer/counter output enable flag TOEn controls output from timer/counter to the TCLOn pin. TOEn is
addressable by 1-bit read and write instructions.
Bit 3
Bit 2
Bit 1
Bit 0
F92H
TOE1
TOE0
BOE
0
When you set the TOEn flag to "1", the contents of TOLn can be output to the TCLOn pin. Whenever a
RESET
occurs, TOEn is automatically set to logic zero, disabling all TC output. Even when the TOE0 flag is disabled,
timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock
selector circuit.
TC OUTPUT LATCH (TOLn)
TOLn is the output latch for timer/counter 0 and 1. When the 8-bit comparator detects a correspondence between
the value of the counter register TCNTn and the reference value stored in the TREFn register, the TOLn value is
inverted — the latch toggles high-to-low or low-to-high. Whenever the state of TOLn is switched, the TC signal is
output. TC output may be directed to the TCLOn pin. TC0 signal can also be output directly to the serial I/O clock
selector circuit as the
SCK signal.
Assuming TC is enabled, when bit 3 of the TMODn register is set to "1", the TOLn latch is cleared to logic zero,
along with the counter register and the interrupt request flag, IRQTn, and counting resumes immediately. When
TCn is disabled (TMODn.2 = "0"), the contents of the TOLn latch are retained and can be read, if necessary.
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