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參數(shù)資料
| 型號(hào)： | S3C7559XX-QT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 20 MM, QFP-64 |
| 文件頁(yè)數(shù)： | 37/197頁(yè) |
| 文件大?。?/td> | 1181K |
| 代理商： | S3C7559XX-QT |
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TIMERS and TIMER/COUNTERS
S3C7559/P7559
11-2
BASIC TIMER (BT)
OVERVIEW
The 8-bit basic timer (BT) has six functional components:
— Clock selector logic
— 4-bit mode register (BMOD)
— 8-bit counter register (BCNT)
— Output enable flag (BOE)
— 8-bit watchdog timer mode register (WDMOD)
— Watchdog timer counter clear flag (WDTCF)
The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.
Timer pulses are output from the basic timer's counter register BCNT to the output pin BTCO when an overflow
occurs in the counter register BCNT. You can use the basic timer as a "watchdog" timer for monitoring system
events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and after a
RESET. Bit settings in the basic timer mode register BMOD turns the BT module on and off, selects the input
clock frequency, and controls interrupt or stabilization intervals.
Interval Timer Function
The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to
256 basic timer clock pulses.
To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD is set to logic one. The
input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values
to BMOD.2–BMOD.0.
The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the
frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs (
255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated
time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting
continues from 00H.
Watchdog Timer Function
The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation
error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper
points in a program within given period. If an instruction that clears the watchdog timer is not executed within the
given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset
status. An operation of watchdog timer is as follows:
— Write some values (except #5AH) to watchdog timer mode register, WDMOD
— If WDCNT overflows, system reset is generated.
Oscillation Stabilization Interval Control
Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also
determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when stop
mode is released by an interrupt. When a
RESET signal is input, the standard stabilization interval for system
clock oscillation after a the
RESET is 36.6 ms at 3.58 MHz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S-3-C-7-D S/C SS SPGS | 功能描述:觸點(diǎn)探頭 HEADLESS FLAT STAINLESS STEEL SPGS RoHS:否 制造商:IDI 類型:Probes 尖端類型:Spherical Radius 長(zhǎng)度:8.26 mm 電流額定值:10 A 彈力:2.3 oz 行程:1.52 mm 系列:101050 |
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