
xxviii
S3C2440A MICROCONTROLLER
List of Figures
(Continued)
Figure
Number
Title
Page
Number
27-11
External Bus Request in ROM/SRAM Cycle
(Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-14
ROM/SRAM READ Timing Diagram (I)
(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)...............................................27-15
ROM/SRAM READ Timing Diagram (II)
(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) .......................................27-16
ROM/SRAM WRITE Timing Diagram (I)
(Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0...................................................27-17
ROM/SRAM WRITE Timing Diagram (II)
(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)...............................................27-18
External nWAIT READ Timing Diagram
(Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19
External nWAIT WRITE Timing Diagram
(Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19
Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11).......27-20
Masked-ROM Consecutive READ Timing Diagram
(Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11)...........................................................27-20
SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit)....................27-21
External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2).............................27-22
SDRAM MRS Timing Diagram..........................................................................................27-23
SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) .........................................27-24
SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3).........................................27-25
SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4).........................................................27-26
SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2)..................................27-27
SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) ..........................................................27-28
SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) ........................................................27-29
SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2)...................................27-30
External DMA Timing Diagram (Handshake, Single transfer)................................................27-31
TFT LCD Controller Timing Diagram...................................................................................27-31
IIS Interface Timing Diagram.............................................................................................27-32
IIC Interface Timing Diagram.............................................................................................27-32
SD/MMC Interface Timing Diagram....................................................................................27-33
SPI Interface Timing Diagram (CPHA=1, CPOL=1) .............................................................27-33
NAND Flash Address/Command Timing Diagram ...............................................................27-34
NAND Flash Timing Diagram............................................................................................27-34
27-12
27-13
27-14
27-15
27-16
27-17
27-18
27-19
27-20
27-21
27-22
27-23
27-24
27-25
27-26
27-27
27-28
27-29
27-30
27-31
27-32
27-33
27-34
27-35
27-36
27-37