參數(shù)資料
型號(hào)： S3C1860XX-DK
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP20
封裝： 0.300 INCH, DIP-20
文件頁(yè)數(shù)： 57/95頁(yè)
文件大?。?/td> 339K
代理商： S3C1860XX-DK
S3C1840/C1850/C1860/P1860
REMOTE CONTROL TX. APPLICATION NOTE
7-3
Auto-Reset
The auto-reset function resets the CPU every 131,072 oscillator cycles (288 ms at fxx = 455 kHz). The auto-reset
counter is cleared when a rising edge is detected at IP2.0, or by a
HALT or RESET pulse.
Normal Mode
Halt
Halt Release Signal
IP2.12 = 1, Non-Active Input Pin
fXX = 455 kHz
Osc. Stabilization Time
(9 ms)
Osc. Circuit
Wait Time
(3-4 ms)
XO
Osc. Stabilization counter starts
Auto-reset
counter
Chip restarts and auto-reset
counter is incremented.
Chip holds it's internal status.
Upon entering Halt mode, the auto-reset counter is
cleared to zero.
Systerm reset occurs when the auto-reset counter
overflows. The program restarts from 0F00hH
Overflow
IP2.0
Normal Mode:
After a reset, the program restart
from 0F00H after one instruction in
0FxxH is executed.('F' is page
number and 'xx' is the next
instruction of HALT instruction)
Chip restarts and the auto-reset counter is incremented
(Reset by internal POR or OSR)
Abnormal
status
VDD
Figure 7-2. Auto-Reset Counter Function
NOTE : The OSR(Oscillation Start and reset) is not implemented for the S3C1840/C1850.
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