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參數(shù)資料
| 型號(hào)： | S3076 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時(shí)鐘恢復(fù)單元) |
| 中文描述： | 多速率SONET / SDH時(shí)鐘恢復(fù)單元（多速率SONET / SDH的時(shí)鐘恢復(fù)單元） |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大小： | 157K |
| 代理商： | S3076 |
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S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.
f0
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
SONET JITTER CHARACTERISTICS
Performance
The S3076 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used as specified.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in Fig-
ure 4. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 7. when
a serial data input with no jitter is presented to the
serial data inputs. (See Table 7.)
S
T
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O
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H
(
)
1
H
(
)
2
H
(
)
3
H
)
k
t
H
)
k
8
4
0
1
0
0
6
0
0
0
6
0
0
1
0
0
0
1
4
2
3
2
1
0
1
0
3
0
0
3
5
2
0
5
2
3
0
1
0
3
0
0
3
5
5
6
S
T
2
S
l
v
e
/
C
O
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)
k
P
B
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8
4
0
0
0
2
1
4
2
3
2
1
0
0
5
1
3
0
3
1
1
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
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