參數(shù)資料
型號(hào)： S3067
廠商： Applied Micro Circuits Corp.
英文描述： Multirate SONET/SDH/ATM Transceiver with FEC(帶正向糾錯(cuò)功能的多速率SONET/SDH/ATM收發(fā)器)
中文描述： 多速率的SONET / SDH / ATM的收發(fā)器與前向糾錯(cuò)（帶正向糾錯(cuò)功能的多速率的SONET / SDH / ATM的收發(fā)器）
文件頁(yè)數(shù)： 6/27頁(yè)
文件大?。?/td> 246K
代理商： S3067
6
S3067
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC
October 26, 2000/ Revision A
S3067 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3067 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48/STS-24/STS-12/STS-3/GBE data stream
depending on the data rate selected. It converts 16
bit parallel data to bit serial format.
A high-frequency bit clock can be generated from a
155.52 to 178 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
other operating modes.
The bypass signal selects between the BYPASSCLK
and the VCO clock. BYPASSCLK can be used to
provide an alternative clock to the internal VCO
when the user selects an error correcting capability
which is not provided by the S3067 dividers. The
user must provide the required frequency for the
BYPASSCLK when error correcting capability of 6/5/
4/3 bytes per 255-byte block is selected.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figures 4 and 5, is a monolithic PLL that generates
the serial output clock frequency locked to the input
Reference Clock (REFCLKP/N).
The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy of
better than the value stated in Table 10 in order for
the TSCLK frequency to have the same accuracy
required for operation in a SONET system. Lower
accuracy crystal oscillators may be used in applica-
tions less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The divide by 'N' and divide by 'M' provide the
counters required to support error correcting capabil-
ity. The values of 'N' and 'M' can be selected by
FECSEL lines.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function, seen in Figure 4,
provides a divide-by-16 version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[15:0] data from
the parallel input register to the serial shift register.
The PCLK output is a divide-by-16 rate version of
transmit serial clock (divide-by-16). PCLK is in-
tended for use as a divide-by-16 clock for upstream
multiplexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3067 device.
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the reference clock REFCLK. The PLL in
the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the
internal clock with that of the Reference Clock
(REFCLK).
Table 5. Reference Jitter Limits
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